MemCon 2024 Agenda

Memory Con

March 2025

Silicon Valley, CA

MemCon 2024 Agenda

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Tuesday, 26 Mar, 2024

9:00AM

Arrival & Registration

Session 1: Re-focusing Memory in a Data-First World

10:00AM

Opening Keynote: How Data and Workloads are Changing the Design of Systems, Clusters and Datacenters

Systems Infrastructure/Architecture

Hyperscaler

Data & Workloads

Author:

Zaid Kahn

VP & GM, Cloud AI & Advanced Systems

Microsoft

Zaid is currently GM in Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.

Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.

Read more about Opening Keynote: How Data and Workloads are Changing the Design of Systems, Clusters and Datacenters

10:25AM

Partner Keynote: Leading HBM and CXL Innovations in the AI Era For High Memory Bandwidth & High Capacity Fulfillment

HBM

CXL

Interconnects

AI/ML Compute

Author:

Jin-Hyeok Choi

Corporate EVP, Device Solution Research America - Memory

Samsung Electronics

Jin-Hyeok Choi leads Device Solution’s R&D – Memory division, which develops new memory technologies and enables memory products.

Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.

Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.

Author:

SangJoon Hwang

Corporate EVP, Head of DRAM Product & Technology

Samsung Electronics

SangJoon Hwang received B.S, M.S., and Ph.D. degrees in electric engineering from the Korea University in 1994, 1996, and 2008, respectively.

He joined the Samsung Electronics, Hwaseong, South Korea in 1996, where he had successfully led a DRAM design group in 2014 and the Flash design team in 2017 as a Vice President and the Memory Product Planning team in 2019 as as a Senior Vice President. Through leading various backgounds from product planning to design, his experience enhances the overall quality of Samsung DRAM products.

Since 2023, he has been leading the DRAM Product & Technology of the Samsung memory division. His current research interests include architecture for next-generation DRAM and product development utilizing new process technology for new product line-up.

Author:

Paul Turner

VP

Broadcom/VMWare

Paul Turner, is the Vice President of the vSphere Product Management team, covering vCenter, ESXi, vMotion and Project Pacific. He is leading our next generation of vSphere and moving the platform to become the leading infrastructure platform for all apps – VMs, Containers and Machine Learning applications. Paul brings more than 20 years expertise in enterprise software product management and marketing - having held leadership roles at VMware, NetApp, Oracle, Cloudian and Scality. Under his leadership, Scality was recognized as a leader in Gartner's Magic Quadrant and also by IDC in their Marketscape report for Object Storage. Prior to this at NetApp, he led the product management and technical marketing for their management software and also ran the Product Strategy Office, where he guided their investments into all-flash, Iongrid, CacheIQ, Onaro and Akorri. 

Paul holds an computer science degree from Trinity College in Ireland. He lives in Los Altos, Silicon Valley with his wife Kristy and their children Conor and Aoife..

Author:

Gunnar Hellekson

VP & GM

RedHat

Gunnar Hellekson is Vice President and General Manager for the Red Hat Enterprise Linux business. Before that, he was Chief Strategist for Red Hat’s US Public Sector group. He is a founder of Open Source for America, one of Federal Computer Week’s Fed 100 for 2010, and was voted one of the FedScoop 50 for industry leadership. He was a founder of the Military Open Source working group, a member of the SIIA Software Division Board, the Board of Directors for the Public Sector Innovation Group, the Open Technology Fund Advisory Council, New America’s California Civic Innovation Project Advisory Council, and the CivicCommons Board of Advisors. He perks up when people talk about commoditization and the industrial mobilization of World War II. He is also co-host of the Dave and Gunnar Show.

Prior to joining Red Hat, he worked as a developer, systems administrator, and IT director for a number of Internet businesses. He has also been a business and IT consultant to not-for-profit organizations in New York City. During that time, he spearheaded the reform of safety regulations for New York State’s electrical utilities through the Jodie Lane Project.

Gunnar’s CV is available in HTML, PDF, and on GitHub.

Read more about Partner Keynote: Leading HBM and CXL Innovations in the AI Era For High Memory Bandwidth & High Capacity Fulfillment

10:55AM

Networking Break

11:40AM

Partner Keynote: Software-Defined Memory is Here: It Performs like Local Memory, Scales, and Works on any Hardware

We all know about the challenges of the “memory wall”. But how can you get over it?

In this talk, Kove and Red Hat will show how Software-Defined Memory has arrived. Red Hat will provide the support drawing from empirical test results of Kove:SDM™ on Supermicro hardware with Red Hat OpenShift using StressNG and Intel P-States.

The data show power savings from 12-54%, near-local CPU performance, and superior performance from remote memory compared to local memory. We’ll show Kove’s pooled memory solution Kove:SDM™ works on standard, existing infrastructure, with no code changes.

We’ll close with a leading expert from Swift discussing how they are changing the game for preventing economic crime for their customers with Kove:SDM™, where the stakes couldn’t be higher.

Software-Defined

New Memory Architectures

Systems Infrastructure/Architecture

Author:

John Overton

CEO

Kove

John Overton is the CEO of Kove IO, Inc. In the late 1980s, while at the Open Software Foundation, Dr. Overton wrote software that went on to be used by approximately two thirds of the world’s workstation market. In the 1990s, he co-invented and patented technology utilizing distributed hash tables for locality management, now widely used in storage, database, and numerous other markets. In the 2000s, he led development of the first truly capable Software-Defined Memory offering, Kove:SDM™. Kove:SDM™ enables new Artificial Intelligence and Machine Learning capabilities, while also reducing power by up to 50%. Dr. Overton has more than 65 issued patents world-wide and has peer-reviewed publications across numerous academic disciplines. He holds post-graduate and doctoral degrees from Harvard and the University of Chicago.

Author:

Narendra Narang

Chief Account Technologist, Telecommunications

Red Hat

Author:

Dr. Chalapathy Neti

Head, AI CoE

Swift

He is a seasoned executive with deep experience in AI (Deep Learning, NLP, Speech, Vision), application of AI and Cloud to solve industry problems (e.g. Personalized learning, Precision Medicine, Customer Intelligence, etc.); and in building and incubating advanced technology businesses anchored on AI and Cloud.

Prior to joining SWIFT, Chalapathy held a number of senior management/executive roles at IBM, including VP, IBM Watson Education, responsible for developing a specialized AI platform on Hybrid Cloud for personalized learning; Director of Healthcare Transformation, responsible for launching and leading IBM’s initiative on Healthcare Transformation, leading to the forming of IBM’s Watson Health business unit, and seeding a number of innovative AI-based clinical decision support offerings (e.g. Watson Genomics);

Chalapathy Neti has a Ph.D. from Johns Hopkins University specializing in neural networks (called “Deep Learning”, today). He has over 75+ publications and 30+ patents. He frequently represented IBM in media, trade and academic conferences.

Read more about Partner Keynote: Software-Defined Memory is Here: It Performs like Local Memory, Scales, and Works on any Hardware

12:10PM

Memory Optimizations for Machine Learning

As Machine Learning continues to forge its way into diverse industries and applications, optimizing computational resources, particularly memory, has become a critical aspect of effective model deployment. This session, "Memory Optimizations for Machine Learning," aims to offer an exhaustive look into the specific memory requirements in Machine Learning tasks and the cutting-edge strategies to minimize memory consumption efficiently.
We'll begin by demystifying the memory footprint of typical Machine Learning data structures and algorithms, elucidating the nuances of memory allocation and deallocation during model training phases. The talk will then focus on memory-saving techniques such as data quantization, model pruning, and efficient mini-batch selection. These techniques offer the advantage of conserving memory resources without significant degradation in model performance.
Additional insights into how memory usage can be optimized across various hardware setups, from CPUs and GPUs to custom ML accelerators, will also be presented.

AI/ML Compute

Enterprise Workloads

Author:

Tejas Chopra

Senior Engineer of Software

Netflix

Tejas Chopra is a Sr. Engineer at Netflix working on Machine Learning Platform for Netflix Studios and a Founder at GoEB1 which is the world’s first and only thought leadership platform for immigrants.Tejas is a recipient of the prestigious EB1A (Einstein) visa in US. Tejas is a Tech 40 under 40 Award winner, a TEDx speaker, a Senior IEEE Member, an ACM member, and has spoken at conferences and panels on Cloud Computing, Blockchain, Software Development and Engineering Leadership.Tejas has been awarded the ‘International Achievers Award, 2023’ by the Indian Achievers’ Forum. He is an Adjunct Professor for Software Development at University of Advancing Technology, Arizona, an Angel investor and a Startup Advisor to startups like Nillion. He is also a member of the Advisory Board for Flash Memory Summit.Tejas’ experience has been in companies like Box, Apple, Samsung, Cadence, and Datrium. Tejas holds a Masters Degree in ECE from Carnegie Mellon University, Pittsburgh.

Read more about Memory Optimizations for Machine Learning

12:30PM

Lunch and Networking

Session 2: Investigating Memory-Bound Use Cases

1:45PM

Samsung’s CXL and HBM Solutions For Future Memory Architecture

Emerging Memory Innovations

Systems Infrastructure/Architecture

HBM/CXL

Author:

SangJoon Hwang

Corporate EVP, Head of DRAM Product & Technology Samsung Electronics

Samsung Electronics

SangJoon Hwang received B.S, M.S., and Ph.D. degrees in electric engineering from the Korea University in 1994, 1996, and 2008, respectively.

He joined the Samsung Electronics, Hwaseong, South Korea in 1996, where he had successfully led a DRAM design group in 2014 and the Flash design team in 2017 as a Vice President and the Memory Product Planning team in 2019 as as a Senior Vice President. Through leading various backgounds from product planning to design, his experience enhances the overall quality of Samsung DRAM products.

Since 2023, he has been leading the DRAM Product & Technology of the Samsung memory division. His current research interests include architecture for next-generation DRAM and product development utilizing new process technology for new product line-up.

Author:

Yang Seok Ki

CXL Board of Director, VP and CTO of Memory Solutions Lab

Samsung Electronics

Dr. Yang Seok Ki is a Vice President and CTO of the Memory Solutions Lab (MSL) at Samsung Semiconductor Inc. in San Jose, California. Since joining Samsung in 2011, he has led various advanced development projects including SmartSSD, Key-Value SSD, CXL Memory Expander, Memory Semantic SSD, etc. In addition, he led the NVMe Key Value Standard, SNIA Key Value API, SNIA Computational Storage Architecture and API. He is a CXL board of director and a technical chair of Data Centric Computing workstream of the Open Computing Project (OCP) Future Technology Initiative (FTI). Prior to joining Samsung, he worked for Oracle's Server Technology Group. Prior to his industrial career, he was involved in High Performance Computing (HPC), Grid Computing, and Cloud research at the Institute of Information Sciences at the University of Southern California and the Center for Networked Systems at the University of California, San Diego. He received his Ph.D. in Electrical Engineering and Computer Engineering from Seoul National University, and his Master's and Bachelor's degrees in Computer Engineering from Seoul National University. He also completed the Engineering Leadership Professional Program (ELPP) from the University of California, Berkeley.

Read more about Samsung’s CXL and HBM Solutions For Future Memory Architecture

2:10PM

How are Increased Adoption of CXL, HBM, and Memory Protocol Expected to Change the Way Memory and Storage is Used and Assembled?

Market Analysis

Hyperscaler

Emerging Memory Innovations

Moderator

Author:

Jim Handy

General Director

Objective Analysis

Jim Handy of Objective Analysis has over 35 years in the electronics industry including 20 years as a leading semiconductor and SSD industry analyst. Early in his career he held marketing and design positions at leading semiconductor suppliers including Intel, National Semiconductor, and Infineon. A frequent presenter at trade shows, Mr. Handy is highly respected for his technical depth, accurate forecasts, widespread industry presence and volume of publication. He has written hundreds of market reports, articles for trade journals, and white papers, and is frequently interviewed and quoted in the electronics trade press and other media.

Speakers

Author:

Siddarth Krishnan

MD, Engineering Management

Applied Materials

Siddarth Krishnan is Managing Director, at Applied Materials, with an R&D focus on Materials Engineering for Heterogenous Integration, Power Devices and alternative memories (RERAM, FERAM etc). In his role, Siddarth and his team research ways of building modules that help connect memory chips (such as High Bandwidth memories) with logic chips and chips with other functionality, using 2D, 2.5D and 3D Integration. Prior to working on Heterogenous Integration, Siddarth worked on various other materials engineering areas, such as MicroLED and Analog In Memory Compute. Previously, Siddarth was an engineering manager at IBM, working on High-K/Metal Gate and FinFET devices.

Author:

John Overton

CEO

Kove

John Overton is the CEO of Kove IO, Inc. In the late 1980s, while at the Open Software Foundation, Dr. Overton wrote software that went on to be used by approximately two thirds of the world’s workstation market. In the 1990s, he co-invented and patented technology utilizing distributed hash tables for locality management, now widely used in storage, database, and numerous other markets. In the 2000s, he led development of the first truly capable Software-Defined Memory offering, Kove:SDM™. Kove:SDM™ enables new Artificial Intelligence and Machine Learning capabilities, while also reducing power by up to 50%. Dr. Overton has more than 65 issued patents world-wide and has peer-reviewed publications across numerous academic disciplines. He holds post-graduate and doctoral degrees from Harvard and the University of Chicago.

Author:

Brett Dodds

Senior Director, Azure Memory Devices

Microsoft

Author:

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA

SNIA

Read more about How are Increased Adoption of CXL, HBM, and Memory Protocol Expected to Change the Way Memory and Storage is Used and Assembled?

2:55PM

Networking Break

3:15PM

Will CXL for AI be the Next HBM? A Deep-Dive into CXL Usage Models - Expansion, Tiering, Pooling and More

Market Analysis

Hyperscaler

Emerging Memory Innovations

Author:

Hoshik Kim

VP & Fellow of Memory Systems Research

SK Hynix

Author:

Siamak Tavallaei

Senior Principal Engineer, System Architecture

Samsung

Siamak Tavallaei joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. In 2016, he joined Open Compute Project (OCP) as a co-lead of Server Project. He is currently the Incubation Committee Representative for the Server Project where he drives open-sourced modular design concepts for integrated hardware/software solutions. He has served as Chief Systems Architect at Google Cloud Platforms where he led the architecture and productization of CXL-enabled solutions. His recent focus has been the optimization of large-scale, mega-datacenters for general-purpose and tightly-connected accelerated machines built on co-designed hardware, software, security, and management. His experiences as Chief Systems Architect at Google Cloud, Senior Principal Architect at Microsoft Azure’s Hardware Architecture team, a Distinguished Technologist at HP, a Principal Member Technical Staff at Compaq, and his contributions to industry collaborations such as CXL, OCP, EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

Author:

David Emberson

Senior Distinguished Technologist

HPE

David Emberson is Senior Distinguished Technologist for HPC System Architecture, where he is working on future memory system designs for HPE Cray systems. He began his career at MIT's Digital Systems Laboratory, where he built one of the first portable computers in 1975. He has held positions at Prime Computer, Megatest, Ametek Computer Research, and Sun Microsystems. At Sun, Mr. Emberson was a member of the SPARC architecture committee, managed the SparcStation 10 and SparcStation 20 programs, and was Senior Director at SunLabs. His consulting clients have included the Hypertransport Consortium, AMD, Intel, Atheros, PathScale, Qlogic and numerous startup companies.

At HPE he was Technical Director of HPE's PathForward program for the Department of Energy's Exascale Computing Program. His current research is in memory system design for HPC systems. He serves on the JEDEC J42.2 (HBM) committee and is a Senior Member of IEEE. Mr. Emberson has a B.S. in Electrical Engineering from MIT. He holds nineteen patents.

Read more about Will CXL for AI be the Next HBM? A Deep-Dive into CXL Usage Models - Expansion, Tiering, Pooling and More

4:00PM

Data Movement for Enterprise Teams – AI Challenges: Latency, Performance and Failing AI Training Scenarios

There are a set of challenges that emanate from memory issues in GenAI deployments in enterprise
• Poor tooling for performance issues related from GPU and memory interconnectedness
• Latency issues as a result of data movement and poor memory capacity planning
• Failing AI training scenarios in low memory constraints

There is both opacity and immature tooling to manage a foundational infrastructure for GenAI deployment, memory. This is experienced by AI teams who need to double-click on the infrastructure and improve on these foundations to deploy AI at scale.

Data Movement/Demands

AI/ML Compute

Enterprise Workloads

Author:

Rodrigo Madanes

Global AI Innovation Officer

EY

Rodrigo Madanes is EY’s Global Innovation AI Leader. Rodrigo has a computer science degree from MIT and a PhD from UC Berkeley. Some testament to his technical expertise includes 3 patents and having created novel AI products at both the MIT Media Lab as well as Apple’s Advanced Technologies Group.

Prior to EY, Rodrigo ran the European business incubator at eBay which launched new ventures including eBay Hire. At Skype, he was the C-suite executive leading product design globally during its hyper-growth phase, where the team scaled the userbase, revenue, and profits 100% YoY for 3 consecutive years.

Author:

Angela Yeung

VP of Product Management

Cerebras Systems

Read more about Data Movement for Enterprise Teams – AI Challenges: Latency, Performance and Failing AI Training Scenarios

4:20PM

Memory & Data Challenges: HPC/AI - View from the Energy Industry

Shell Upstream has been processing large subsurface datasets for multiple decades driving significant business value. Many of the state of the art algorithms for this have been developed using deep domain knowledge and have benefitted from the hardware technology improvements over the years. However, the demand for more efficient processing as datasets get bigger and the algorithms become even more complex is ever-growing. This talk will focus on the memory and data management challenges for a variety of traditional HPC workflows in the energy industry. It will also cover unique challenges for accelerating modern AI-based workflows requiring new innovations.

AI/ML Compute

Enterprise Workloads

HPC

Author:

Dr. Vibhor Aggarwal

Manager: Digital & Scientific HPC

Shell

Vibhor is an R&D leader with expertise in HPC Software, Scientific Visualization, Cloud Computing and AI technologies with 14 years of experience. He and his team at Shell are currently work on problems in optimizing HPC software for simulations, large-scale and generative AI, combination of Physics and AI models, developing platform and products for HPC-AI solutions as well as emerging HPC areas for energy transition at the forefront of Digital Innovation. He has two patents and several research publications. Vibhor has a BEng in Computer Engineering from University of Delhi and a PhD in Engineering from University of Warwick.

Read more about Memory & Data Challenges: HPC/AI - View from the Energy Industry

4:40PM

Addressing the Memory Wall in Die-to-Memory Chiplet Interconnect

Compute performance demand has been growing exponentially in recent years, and with the advent of Generative AI, this demand is growing even faster. Moore’s law coming to an end as well as the Memory Wall (bandwidth & capacity) are the main performance bottlenecks. The chiplet system-in-package (SiP) is the industry's solution to these bottlenecks. Silicon interposers are industry’s main technology to connect chiplets in SiPs, but they introduce several new bottlenecks. The largest interposer going to production is 2700mm2, which is ~1/4 the largest standard package substrate. Thus, a SiP with silicon interposer has limited compute & memory chiplets, thus limited performance.
This presentation introduces Universal Memory Interface (UMI), a high bandwidth efficient D2D connectivity technology between compute and memory chiplets. UMI PHY on standard packaging provides similar bandwidth/power to D2D PHYs with silicon interposers, thus enables creation of large & powerful SiPs required to address Gen AI applications.

Emerging Memory Innovations

Interconnects

Author:

Ramin Farjadrad

Co-Founder & CEO

Eliyan

Ramin Farjadrad is the inventor of over 130 granted and pending patents in communications and networking. He has a successful track record of creating differentiating connectivity technologies adopted by the industry as International standards (Two Ethernet standards at IEEE, one chiplet connectivity at OCP.) Ramin co-founded Velio Communications, which led to a Rambus/LSI Logic acquisition, and Aquantia, which IPO’d and was acquired by Marvell Technologies. Ramin’s Ph.D. EE is from Stanford.

Read more about Addressing the Memory Wall in Die-to-Memory Chiplet Interconnect

5:05PM

Networking Break

Session 3: Trade-offs and Roadmaps in Reducing Friction-Points in New Technology Adoption

5:30PM

How to Improve Data Movement using Accelerated Networks?

Data Movement/Demands

Systems Infrastructure/Architecture

AI/ML Compute

Moderator

Author:

Mahesh Wagh

Senior Fellow & Server System Architect

AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Speakers

Author:

Paul Crumley

Senior Technical Staff Member

IBM Research

Paul G Crumley, a Senior Technical Staff Member at IBM Research, enjoys creating systems to solve problems beyond the reach of current technology.

Paul’s current project integrates secure, compliant AI capabilities with enterprise Hybrid Cloud allowing clients to extract new business value from their data.

Paul’s previous work includes the design and construction of distributed, and high-performance computing systems at CMU, Transarc, and IBM Research. Projects include The Andrew Project at CMU, ASCI White, IBM Global Storage Architecture, Blue Gene Supercomputers, IBM Cloud, and IBM Cognitive Systems. Paul has managed data centers, and brings his first-hand knowledge of these environments, combined with experience of automation and robustness, to the design of AI for Hybrid Cloud infrastructure.

Author:

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel

CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Author:

Manoj Wadekar

Hardware Systems Technologist

Meta

Read more about How to Improve Data Movement using Accelerated Networks?

6:15PM

Enabling Generative AI with Oracle AI Vector Search

Oracle AI Vector Search enables enterprises to leverage their own business data to build cutting-edge generative AI solutions. AI Vectors are data structures that encode the key features or essence of unstructured entities such as images or documents. The more similar two entities are, the shorter the mathematical distance between their corresponding AI vectors. With AI Vector search, Oracle Database is introducing a new vector datatype, new vector indexes (in-memory neighbor graph indexes and neighbor partitioned indexes), and new Vector SQL operators for highly efficient and powerful similarity search queries. Oracle AI Vector Search enables applications to combine their business data with large language models (LLMs) using a technique called Retrieval Augmentation Generation (RAG), to deliver amazingly accurate responses to natural language questions. With AI Vector Search in Oracle Database, users can easily build AI applications that combine relational searches with similarity search, without requiring data movement to a separate vector database, and without any loss of security, data integrity, consistency, or performance. At the heart of this are the hardware and system requirements needed to facilitate scale up and scale out AI vector search.

Emerging Memory Innovations

Systems Infrastructure/Architecture

Author:

Tirthankar Lahiri

SVP, Data & In-Memory Technologies

Oracle

Tirthankar Lahiri is Vice President of the Data and In-Memory Technologies group for Oracle Database and is responsible for the Oracle Database Engine (including Database In-Memory, Data and Indexes, Space Management, Transactions, and the Database File System), the Oracle TimesTen In-Memory Database, and Oracle NoSQLDB. Tirthankar has 22 years of experience in the Database industry and has worked extensively in a variety of areas including Manageability, Performance, Scalability, High Availability, Caching, Distributed Concurrency Control, In-Memory Data Management, NoSQL architectures, etc. He has 27 issued and has several pending patents in these areas. Tirthankar has a B.Tech in Computer Science from the Indian Institute of Technology (Kharagpur) and an MS in Electrical Engineering from Stanford University.

Read more about Enabling Generative AI with Oracle AI Vector Search

6:35PM

End of Day One

Wednesday, 27 Mar, 2024

09:00AM

Arrival & Registration

Session 4: Delivering at Scale - Separation of Compute Powers & The Impact on Memory Architectures

10:00AM

The Evolution of Hyperscale Data Centers: From CPU-Centric to GPU-Accelerated AI Applications

In recent years, hyperscale data centers have been optimized for scale-out stateless applications and zettabyte storage, with a focus on CPU-centric platforms. However, as the infrastructure shifts towards next-generation AI applications, the center of gravity is moving towards GPU/accelerators. This transition from "millions of small stateless applications" to "large AI applications running across clusters of GPUs" is pushing the limits of accelerators, network, memory, topologies, rack power, and other components. To keep up with this dramatic change, innovation is necessary to ensure that hyperscale data centers can continue to support the growing demands of AI applications. This keynote speech will explore the challenges and opportunities of this evolution and highlight the key areas where innovation is needed to enable the future of hyperscale data centers.

Systems Infrastructure/Architecture

AI/ML Compute

Author:

Manoj Wadekar

Hardware Systems Technologist

Meta

Read more about The Evolution of Hyperscale Data Centers: From CPU-Centric to GPU-Accelerated AI Applications

10:25AM

How AI 2.0 Will Shape the Memory Landscape

AI 1.0 is ubiquitous in today’s world characterized by voice assistants, recommendation engines and search platforms. With the rise of generative AI, we are now firmly on the journey to the next frontier: AI 2.0. Generative AI applications are increasing in sophistication at a lightning pace, and we are witnessing the beginning of AI democratization through highly accessible user interfaces and open source development tools. This presentation will look at the implications of AI 2.0 across the hardware landscape, from data center, edge and end points, with a particular focus on how AI 2.0’s voracious needs for greater bandwidth and capacity will shape the evolution of memory sub-systems and technology.

Systems Infrastructure/Architecture

AI/ML Compute

Author:

Matt Jones

VP of Strategic Marketing

Rambus

Matt Jones joined Rambus in 2019 and currently serves as the Vice President of Strategic Marketing at Rambus. He is responsible for development and growth of the company’s silicon and IP products, driving high-performance, secured memory and interconnect architectural innovation in Data Center and Edge Connectivity applications. Prior to his current role, Matt served as General Manager for the company’s IP Cores business unit. Before joining Rambus, Matt held various product line management and marketing positions for microprocessor, connectivity, and power management products over a twenty-four-year career at IDT, later acquired by Renesas. Matt holds a Bachelor of Science in Electrical Engineering and a Bachelor of Arts in Economics from Stanford University.

Read more about How AI 2.0 Will Shape the Memory Landscape

10:50AM

Memory Optimizations for Large Language Models: From Training to Inference

Large Language Models (LLMs) have revolutionized natural language processing but have posed significant challenges in training and inference due to their enormous memory requirements. In this talk, we delve into techniques and optimizations to mitigate memory constraints across the entire lifecycle of LLMs.

The first segment explores Memory Optimized LLM Training. We discuss Training challenges and cover different techniques under Parameter Efficient Fine Tuning (PEFT). like prompt tuning with LoRA, and adapters.

LLMs inference is more memory bound rather than compute bound, In this section we will explore inference optimizations mostly for transformer architectures like Paged Key-Value (KV) Cache, Speculative Decoding, Quantization, Inflight Batching strategies, Flash Attention, each contributing to enhanced inference speed and efficiency.

Finally, we explore the concept of Coherent Memory, and how it helps with Inference optimizations by KV Cache offloading and LoRA weight re-computation.

By illuminating these advancements, this talk aims to provide a comprehensive understanding of state-of-the-art memory optimization techniques for LLMs, empowering practitioners to push the boundaries of natural language processing further.

Systems Infrastructure/Architecture

AI/ML Compute

Author:

Arun Raman

Deep Learning Solutions Architect

NVIDIA

Arun Raman is an AI solution architect at NVIDIA, adept at navigating the intricate challenges of deploying AI applications across edge, cloud, and on-premises environments within the consumer Internet industry. In his current role, he works on the design of end-to-end accelerated AI pipelines, for consumer internet customers meticulously addressing preprocessing, training, and inference optimizations. His experience extends beyond AI, having worked with distributed systems and multi-cloud infrastructure. He shares practical strategies and real-world experiences, empowering organizations to leverage AI effectively.

Read more about Memory Optimizations for Large Language Models: From Training to Inference

11:15AM

Networking Break

12:00PM

Scaling Genomics Computations and Adapting to New Architectures

As the cost of sequencing drops and the quantity of data produced by sequencing grows, the amount of processing dedicated to genomics is increasing at a rapid pace. [Genomics is evolving in a number of directions simultaneously.] Complex pipelines are written in such a manner that they are portable to either clusters or clouds. Key kernels are also being ported to GPUs in a drop-in replacement for their non-accelerated counterpart. These techniques are helping to address challenges of scaling up genomics computations and porting validated pipelines to new systems. However, all of these computations strain the bandwidth and capacity of available resources. In this talk, Roche´s Tom Sheffler will share an overview of the memory-bound challenges present in genomics and venture some possible solutions.

Author:

Tom Sheffler

Solution Architect, Next Generation Sequencing

Roche

Tom earned his PhD from Carnegie Mellon in Computer Engineering with a focus on parallel computing architectures and prrogramming models. His interest in high-performance computing took him to NASA Ames, and then to Rambus where he worked on accelerated memory interfaces for providing high bandwidth. Following that, he co-founded the cloud video analytics company, Sensr.net, that applied scalable cloud computing to analyzing large streams of video data. He later joined Roche to work on next-generation sequencing and scalable genomics analysis platforms. Throughout his career, Tom has focused on the application of high performance computer systems to real world problems.

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12:20PM

Evaluating the Potential of Disaggregated Memory Systems for HPC Applications

Disaggregated memory is a promising approach that addresses the limitations of traditional memory architectures by enabling memory to be decoupled from compute nodes and shared across a data center. Cloud platforms have deployed such systems to improve overall system memory utilization, but performance can vary across workloads. High-performance computing (HPC) is crucial in scientific and engineering applications, where HPC machines also face the issue of underutilized memory. As a result, improving system memory utilization while understanding workload performance is essential for HPC operators. Therefore, learning the potential of a disaggregated memory system before deployment is a critical step. This paper proposes a methodology for exploring the design space of a disaggregated memory system. It incorporates key metrics that affect performance on disaggregated memory systems: memory capacity, local and remote memory access ratio, injection bandwidth, and bisection bandwidth, providing an intuitive approach to guide machine configurations based on technology trends and workload characteristics. We apply our methodology to analyze thirteen diverse workloads, including AI training, data analysis, genomics, protein, fusion, atomic nuclei, and traditional HPC bookends. Our methodology demonstrates the ability to comprehend the potential and pitfalls of a disaggregated memory system and provides motivation for machine configurations. Our results show that eleven of our thirteen applications can leverage injection bandwidth disaggregated memory without affecting performance, while one pays a rack bisection bandwidth penalty and two pay the system-wide bisection bandwidth penalty. In addition, we also show that intra-rack memory disaggregation would meet the application's memory requirement and provide enough remote memory bandwidth.

Systems Infrastructure/Architecture

HPC

Emerging Memory Innovations

Author:

Nan Ding

Research Scientist

Berkeley Research Lab

Nan Ding is a Research Scientist in the Performance and Algorithms group of the Computer Science Department at Lawrence Berkeley National Laboratory. Her research interests include high-performance computing, performance modeling and performance optimization. Nan received her Ph.D. in computer science from Tsinghua University, Beijing, China in 2018.

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12:40PM

Breaking Memory Bottlenecks: Unleashing AI Compute and Connectivity with Chiplet-Enabled Custom Silicon

Generative AI is reshaping compute and connectivity by pushing the limits of today's semiconductors. A new era of custom silicon designs has emerged, and is being embraced by all the major hyper-scalers. Chiplets in advanced 2.5D/3D packaging with high-speed interfaces such as HBM, UCIe, PCIe/CXL, and Ethernet have become key to address the critical challenges of memory bottlenecks for AI workloads. Learn how Alphawave Semi’s custom silicon and chiplet platforms are paving the way for unprecedented levels of performance, power efficiency, and scalability in AI-driven applications.

Author:

Mohit Gupta

SVP and GM, Custom Silicon and IP

Alphawave Semi

Mohit Gupta joined Alphawave Semi in September 2022 as part of the OpenFive acquisition from SiFive. He currently serves as Senior Vice President and General Manager for IP and Custom Silicon Business unit. Mohit brings in more than 2 decades of experience in semiconductor IP and SoC domains leading worldwide engineering, application engineering, products, and field teams. Prior to Alphawave Semi, he led the IP and Custom SoC business units at SiFive and Rambus.

Mohit holds a Bachelor of Engineering in Electronics and Communications from Thapar University and Master of Science in Microelectronics from BITS, Pilani. He also holds an executive MBA in International Business from Indian Institute of Management, Calcutta.

Read more about Breaking Memory Bottlenecks: Unleashing AI Compute and Connectivity with Chiplet-Enabled Custom Silicon

12:40PM

Lunch and Networking

Session 5: Co-Designing the Heterogeneous Compute Future

2:20PM

The Role of Memory in Heterogeneous Computing to Support AI/ML and High Performance (HPC) Workloads

The computing world is looking to heterogeneous computing to solve many important problems in AI/Machine Learning (ML) and high-performance computing (HPC). The term “heterogenous compute” refers to the use of groups of processors that are based on different types of computer architectures. This occurs in cases where a particular architecture is better suited for a specific task due to energy-efficiency, task optimization, or the number of cores available in the processors. The inherent parallelism of working with multiple CPUs, GPUs, ASICs, FPGAs, and NPUs is driving customers’ wider use of expanded memory and "memory pools" to support these scalable, heterogeneous computing workloads. This panel will cover the value points for heterogeneous computing including performance, operational efficiency and energy-efficiency.

AI/ML Compute

Software/Hardware

Systems Infrastructure/Architecture

Moderator

Author:

Jean Bozman

President

Cloud Architects Advisors, LLC

Jean S. Bozman is an IT industry analyst focusing on cloud infrastructure and the proud founder of a new company, Cloud Architects Advisors LLC.

She has had experience as an IDC Research VP for 10+ years and has covered the semiconductor industry as an analyst for over 20 years.

Speakers

Author:

James Ang

Chief Scientist for Computing

Pacific Northwest National Lab

Jim is the Chief Scientist for Computing in the Physical and Computational Sciences Directorate (PCSD) at Pacific Northwest National Laboratory (PNNL). Jim’s primary role is to serve as PNNL’s Sector Lead for the DOE/SC Advanced Scientific Computing Research (ASCR) Office. At PNNL, the ASCR portfolio includes over a dozen R&D projects in computer science, applied mathematics, networking, and computational modeling and simulation. Jim also serves as the lead of the Data-Model Convergence Initiative, a lab-wide 5 year investment to develop new computer science capabilities that support integration of scientific high performance computing and data analytics computing paradigms. Through a co-design process, challenge problems that integrate scientific modeling and simulation, domain-aware machine learning, and graph analytics are used to drive the development of a supporting system software stack that maps these heterogeneous applications to conceptual designs for System-on-Chip (SoC) heterogeneous processors. A key element of this converged computing strategy is to support PNNL objectives in accelerating scientific discovery, and real time control of the power grid. Jim's prior connections to other government agencies transferred to PNNL with him and has led to PNNL and Jim's engagement in several national security programs.

Prior to joining PNNL, Jim served as the a member of the initial DOE Exascale Computing Project (ECP) leadership team from 2015-2017. Jim's role was the Director of ECP's hardware technology focus area. His primary role and responsibility was the development and definition of the DOE ECP's hardware R&D strategy. The key elements of the strategy included: 1) Establish a portfolio of PathForward vendor-led hardware R&D projects for component, node and system architecture design, and 2) Create a Design Space Evaluation team to provide ECP with independent architectural analysis of the PathForward vendors' designs and the ability to facilitate co-design communication among the PathForward vendors and the ECP's application and system software development teams.

Author:

Camberley Bates

VP, Practice Lead, Data Infrastructure

The Futurum Group

Author:

Tom Coughlin

President

Coughlin Associates

Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant. He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.

Dr. Coughlin has many publications and six patents to his credit. Tom is also the author of Digital Storage in Consumer Electronics: The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services. Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports. Tom is also a regular contributor on digital storage for Forbes.com and other blogs.

Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations. Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years. He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV). For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.

Read more about The Role of Memory in Heterogeneous Computing to Support AI/ML and High Performance (HPC) Workloads

3:05PM

Indirect/Irregular Workloads within Large Simulations and How to Improve Access through Co-Design

Los Alamos National Laboratory's (LANL) has a diverse set of High Performance Computing codes. Analysis of many of these codes indicate they are heavily memory bound with sparse memory accesses. High Bandwidth Memory (HBM) has proven a significant advancement in improving the performance of these codes but the roadmap for major (step function) improvements in memory technologies is unclear. Addressing this challenge will require a renewed focus on high performance memory and processor technologies that take a more aggressive and holistic view of advancements in ISA, microarchitecture, and memory controller technologies. Beyond scientific simulations, advancements in performance of sparse memory accesses will benefit graph analysis, DLRM inference, and database workloads.

Author:

Galen Shipman

Computer Scientist

Los Alamos National Laboratories

Galen Shipman is a computer scientist at Los Alamos National Laboratory (LANL). His interests include programming models, scalable runtime systems, and I/O. As Chief Architect he leads architecture and technology of Advanced Technology Systems (ATS) at LANL. He has led performance engineering across LANL’s multi-physics integrated codes and the advancement and integration of next-generation programming models such as the Legion programming system as part of LANL's next-generation code project, Ristra. His work in storage systems and I/O is currently focused on composable micro-services as part of the Mochi project. His prior work in scalable software for HPC include major contributions to broadly used technologies including the Lustre parallel file system and Open MPI.

Read more about Indirect/Irregular Workloads within Large Simulations and How to Improve Access through Co-Design

3:30PM

How are Memory Innovations and Power Consumption Impacting the Total Cost of Ownership in Scaling-Up

Hyperscaler

Emerging Memory Innovations

Cost/Power

AI/ML Compute

Moderator

Author:

Shyam Iyer

Distinguished Engineer & Member Of SNIA Technical Council

Dell

Speakers

Author:

David Kanter

Founder & Executive Director

MLCommons

David founded and leads MLCommons, to make machine learning better for everyone through benchmarks, such as MLPerf, and building datasets and tools for data-centric AI.

The mission of MLCommons™ is to make machine learning better for everyone. Together with its 50+ founding Members and Affiliates, including startups, leading companies, academics, and non-profits from around the globe, MLCommons will help grow machine learning from a research field into a mature industry through benchmarks, public datasets and best practices. MLCommons firmly believes in the power of open-source and open data. Our software projects are generally available under the Apache 2.0 license and our datasets generally use CC-BY 4.0.

Author:

Dylan Patel

Chief Analyst

Semi Analysis

Author:

Matthew Burns

Technical Marketing Manager

Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

Author:

Helen Byrne

VP, Solution Architect

Graphcore

Helen leads the Solution Architects team at Graphcore, helping innovators build their AI solutions using Graphcore’s Intelligence Processing Units (IPUs). She has been at Graphcore for more than 5 years, previously leading AI Field Engineering and working in AI Research, working on problems in Distributed Machine Learning. Before landing in the technology industry, she worked in Investment Banking. Her background is in Mathematics and she has a MSc in Artificial Intelligence.

Read more about How are Memory Innovations and Power Consumption Impacting the Total Cost of Ownership in Scaling-Up

4:15PM

Networking Break

4:40PM

Bandits for Large Scale Recommendation Systems

Online commercial app marketplaces serve millions of apps to billions of users in an efficient manner. Bandit optimization algorithms are used to ensure that the recommendations are relevant, and converge to the best performing content over time. However, directly applying bandits to real-world systems, where the catalog of items is dynamic and continuously refreshed, is not straightforward. One of the challenges we face is the non-trivial computation costs for large scale systems, which is further aggravated by user privacy related constraints for server side computation. To address this problem we introduce an efficient two-layer bandit approach which is contextualized to user cohorts of similar taste. We mitigate cannibalization at runtime within a single multi-intent content surfacing platform by formalizing relevant offline evaluation metrics, and by involving the cross-component interactions in the bandit rewards. The framework allows flexibility for tradeoffs between compute, storage and accuracy of models. The user engagement in our proposed system has more than doubled as measured by online A/B testings.

AI/ML Compute

Enterprise Workloads

Data Movement/Demands

Systems Infrastructure/Architecture

Author:

Puja Das

Senior Director, Personalization

Warner Bros. Entertainment

Dr. Puja Das, leads the Personalization team at Warner Brothers Discovery (WBD) which includes offerings on Max, HBO, Discovery+ and many more.

Prior to WBD, she led a team of Applied ML researchers at Apple, who focused on building large scale recommendation systems to serve personalized content on the App Store, Arcade and Apple Books. Her areas of expertise include user modeling, content modeling, recommendation systems, multi-task learning, sequential learning and online convex optimization. She also led the Ads prediction team at Twitter (now X), where she focused on relevance modeling to improve App Ads personalization and monetization across all of Twitter surfaces.

She obtained her Ph.D from University of Minnesota in Machine Learning, where the focus of her dissertation was online learning algorithms, which work on streaming data. Her dissertation was the recipient of the prestigious IBM Ph D. Fellowship Award.

She is active in the research community and part of the program committee at ML and recommendation system conferences. Shas mentored several undergrad and grad students and participated in various round table discussions through Grace Hopper Conference, Women in Machine Learning Program colocated with NeurIPS, AAAI and Computing Research Association- Women’s chapter.

Read more about Bandits for Large Scale Recommendation Systems

5:00PM

Exploring CXL Use Cases and the Future of Disaggregated Heterogeneous Memory Architecture

Compute Express Link (CXL) has risen as a promising interconnect technology that enables seamless high-speed, low-latency communication between host processors and various peripheral devices, making it attractive for memory-intensive applications. In this talk, we'll evaluate the performance characteristics of CXL memory in real-world environments using ASIC-based CXL memory. We then present our learnings from microbenchmarks, explore the potential use cases and evaluate their benefits from using CXL memory. Based on our comprehensive evaluations, we share our insights of how we may better utilize CXL memory to optimize the performance and cost of data center applications, as well as our vision for next-gen memory architecture leveraging new capabilities from CXL 2.0/3.x.

Emerging Memory Innovations

HBM/CXL

Systems Infrastructure/Architecture

Author:

Ping Zhou

Researcher/Architect

Bytedance Ltd.

Ping Zhou is a Senior Researcher/Architect with ByteDance, focusing on next-gen infrastructure innovations with hardware/software co-design. Prior to joining ByteDance, Ping worked with Google, Alibaba and Intel on products including Google Assistant, Optane SSD and Open Channel SSD. Ping earned his PhD in Computer Engineering at University of Pittsburgh, specializing in the field of emerging memory and storage technologies.

Read more about Exploring CXL Use Cases and the Future of Disaggregated Heterogeneous Memory Architecture

5:20PM

How are Compute Architectures and Workloads Impacting the Memory and Systems Market Going Forward?

Moderator

Author:

Simone Bertolazzi

Principal Analyst, Memory

Yole Group

Simone Bertolazzi, PhD is a Senior Technology & Market analyst, Memory, at Yole Intelligence, part of Yole Group, working with the Semiconductor, Memory & Computing division. As member of the Yole’s memory team, he contributes on a day-to-day basis to the analysis of memory markets and technologies, their related materials, device architectures and fabrication processes. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland) and a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.

Speakers

Author:

Ramin Farjadrad

Co-Founder & CEO

Eliyan

Ramin Farjadrad is the inventor of over 130 granted and pending patents in communications and networking. He has a successful track record of creating differentiating connectivity technologies adopted by the industry as International standards (Two Ethernet standards at IEEE, one chiplet connectivity at OCP.) Ramin co-founded Velio Communications, which led to a Rambus/LSI Logic acquisition, and Aquantia, which IPO’d and was acquired by Marvell Technologies. Ramin’s Ph.D. EE is from Stanford.

Author:

Mike Ignatowski

Sr. Fellow

AMD

Michael Ignatowski is a Sr. Fellow, leading AMD’s Research and Advanced Development division in advanced memory technology and architecture for future systems. Prior to joining AMD in 2010, he worked at IBM for 27 years in the mainframe product division and the T.J. Watson Research division in Yorktown. Michael holds over 25 patents, has participated on panel sessions at major conferences, and has given multiple invited talks and keynote presentations.

Read more about How are Compute Architectures and Workloads Impacting the Memory and Systems Market Going Forward?

6:05PM

End of Day Two

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