The computing world is looking to heterogeneous computing to solve many important problems in AI/Machine Learning (ML) and high-performance computing (HPC). The term “heterogenous compute” refers to the use of groups of processors that are based on different types of computer architectures. This occurs in cases where a particular architecture is better suited for a specific task due to energy-efficiency, task optimization, or the number of cores available in the processors. The inherent parallelism of working with multiple CPUs, GPUs, ASICs, FPGAs, and NPUs is driving customers’ wider use of expanded memory and "memory pools" to support these scalable, heterogeneous computing workloads. This panel will cover the value points for heterogeneous computing including performance, operational efficiency and energy-efficiency.
Jean Bozman
Jean S. Bozman is an IT industry analyst focusing on cloud infrastructure and the proud founder of a new company, Cloud Architects Advisors LLC.
She has had experience as an IDC Research VP for 10+ years and has covered the semiconductor industry as an analyst for over 20 years.
James Ang
Jim is the Chief Scientist for Computing in the Physical and Computational Sciences Directorate (PCSD) at Pacific Northwest National Laboratory (PNNL). Jim’s primary role is to serve as PNNL’s Sector Lead for the DOE/SC Advanced Scientific Computing Research (ASCR) Office. At PNNL, the ASCR portfolio includes over a dozen R&D projects in computer science, applied mathematics, networking, and computational modeling and simulation. Jim also serves as the lead of the Data-Model Convergence Initiative, a lab-wide 5 year investment to develop new computer science capabilities that support integration of scientific high performance computing and data analytics computing paradigms. Through a co-design process, challenge problems that integrate scientific modeling and simulation, domain-aware machine learning, and graph analytics are used to drive the development of a supporting system software stack that maps these heterogeneous applications to conceptual designs for System-on-Chip (SoC) heterogeneous processors. A key element of this converged computing strategy is to support PNNL objectives in accelerating scientific discovery, and real time control of the power grid. Jim's prior connections to other government agencies transferred to PNNL with him and has led to PNNL and Jim's engagement in several national security programs.
Prior to joining PNNL, Jim served as the a member of the initial DOE Exascale Computing Project (ECP) leadership team from 2015-2017. Jim's role was the Director of ECP's hardware technology focus area. His primary role and responsibility was the development and definition of the DOE ECP's hardware R&D strategy. The key elements of the strategy included: 1) Establish a portfolio of PathForward vendor-led hardware R&D projects for component, node and system architecture design, and 2) Create a Design Space Evaluation team to provide ECP with independent architectural analysis of the PathForward vendors' designs and the ability to facilitate co-design communication among the PathForward vendors and the ECP's application and system software development teams.
Camberley Bates
Tom Coughlin
Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant. He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.
Dr. Coughlin has many publications and six patents to his credit. Tom is also the author of Digital Storage in Consumer Electronics: The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services. Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports. Tom is also a regular contributor on digital storage for Forbes.com and other blogs.
Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations. Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years. He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV). For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.