MemCon 2023 Agenda | Kisaco Research

MemCon 2023 Agenda

Memory Con
26-27 March, 2024
Computer History Museum, Silicon Valley, CA

See below the agenda from the 2023 event. 

The 2024 agenda will be coming shortly...register your interest here to be the first to know when it is released!


Tuesday, 28 Mar, 2023
09:00 AM
REGISTRATION & EXHIBITS OPEN
09:50 AM - 10:00 AM
OPENING REMARKS

Author:

Jinman Han

Corporate EVP and President of Device Solutions America
Samsung Electronics

Jinman Han serves as President of Samsung Device Solutions Americas (DSA) and Corporate EVP of Samsung Electronics, responsible for Samsung's U.S. semiconductor business, which includes Memory, Foundry, System LSI, and LED.

 

Jinman is a respected leader who has held many leadership positions at Samsung throughout his career, most recently as head of the Memory Global Sales & Marketing team. He joined Samsung in 1989 and has worked in various departments, including DRAM design, Flash design, Flash solution product planning, Memory product planning and application engineering, and SSD development.

 

His expertise and insight in the industry have contributed significantly to the company's presence within the memory market and have helped maintain Samsung's market leadership for decades.

 

Jinman is based in San Jose, CA, and holds a bachelor's degree in Electrical Engineering from Seoul National University in Korea.

Jinman Han

Corporate EVP and President of Device Solutions America
Samsung Electronics

Jinman Han serves as President of Samsung Device Solutions Americas (DSA) and Corporate EVP of Samsung Electronics, responsible for Samsung's U.S. semiconductor business, which includes Memory, Foundry, System LSI, and LED.

 

Jinman is a respected leader who has held many leadership positions at Samsung throughout his career, most recently as head of the Memory Global Sales & Marketing team. He joined Samsung in 1989 and has worked in various departments, including DRAM design, Flash design, Flash solution product planning, Memory product planning and application engineering, and SSD development.

 

His expertise and insight in the industry have contributed significantly to the company's presence within the memory market and have helped maintain Samsung's market leadership for decades.

 

Jinman is based in San Jose, CA, and holds a bachelor's degree in Electrical Engineering from Seoul National University in Korea.

10:00 AM - 10:30 AM
OPENING KEYNOTE
Emerging Memories
External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Zaid Kahn

VP & GM, Cloud AI & Advanced Systems
Microsoft

Zaid is currently GM in Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.

Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.

Zaid Kahn

VP & GM, Cloud AI & Advanced Systems
Microsoft

Zaid is currently GM in Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.

Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.

10:30 AM - 11:00 AM
FOUNDING PARTNER KEYNOTE
Embedded Memory
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Jin-Hyeok Choi

Corporate EVP, Device Solution Research America - Memory
Samsung Electronics

Jin-Hyeok Choi leads Device Solution’s R&D – Memory division, which develops new memory technologies and enables memory products.

Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.

Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.

Jin-Hyeok Choi

Corporate EVP, Device Solution Research America - Memory
Samsung Electronics

Jin-Hyeok Choi leads Device Solution’s R&D – Memory division, which develops new memory technologies and enables memory products.

Jin-Hyeok joined Samsung Electronics in 2003 as a SoC design engineer, working on the development of mobile storage. From 2012 to 2019, he was in charge of the development team for controllers, a core component of SoCs based on NAND Flash. He developed and commercialized the world's first eMMC and UFS products, as well as various controllers for SATA/SAS/NVMe SSDs. He also developed the first-ever enterprise premium SSD with high endurance VNAND and has contributed significantly to the expansion of the storage market.

Jin-Hyeok received his B.S., M.S., and Ph. D. degrees in Electronics Engineering from Seoul National University in 1989, 1991, and 1996, respectively. He also studied low-power circuits at the University of Tokyo's Institute of Industrial Science.

11:00 AM - 11:30 AM
KEYNOTE
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Dimitri Kusnezov

Under Secretary for Science & Technology
Department of Homeland Security

Dr. Dimitri Kusnezov [Kooz-NETS-off] was confirmed as the Under Secretary for the Science and Technology Directorate (S&T) on September 8, 2022. As the science advisor to the Homeland Security Secretary, Dr. Kusnezov heads the research, development, innovation and testing and evaluation activities in support of the Department of Homeland Security’s (DHS) operational Components and first responders across the nation. S&T is responsible for identifying operational gaps, conceptualizing art-of-the-possible solutions, and delivering operational results that improve the security and resilience of the nation. 

Prior to DHS, Dr. Kusnezov was a theoretical physicist working at the U.S. Department of Energy (DOE) focusing on emerging technologies. He served in numerous positions, including the Deputy Under Secretary for Artificial Intelligence (AI) & Technology where he led efforts to drive AI innovation and bring it into DOE missions, business and operations, including through the creation of a new AI Office. 

Dr. Kusnezov has served in scientific and national security positions, including Senior Advisor to the Secretary of Energy, Chief Scientist for the National Nuclear Security Administration, Director of Advanced Simulation and Computing and the Director of the multi-billion-dollar National Security Science, Technology and Engineering programs. He created numerous programs, including for Minority Serving Institutions, international partners, private sector and philanthropic entities. He has worked across agencies to deliver major milestones such as DOE’s 10-year grand challenge for a 100 Teraflop supercomputer, and first of their kind and world’s fastest supercomputers. 

Prior to DOE and his pursuit of public service, Dr. Kusnezov had a long career in academia where he published more than 100 articles and edited two books. He joined Yale University faculty where he was a professor for more than a decade in Theoretical Physics and served as a visiting professor at numerous universities around the world. Before this post, Dr. Kusnezov did a brief postdoc and was an instructor at Michigan State University, following a year of research at the Institut fur Kernphysik, KFA-Julich, in Germany. He earned his MS in Physics and Ph.D. in Theoretical Nuclear Physics at Princeton University and received Bachelor of Arts degrees in Physics and in Pure Mathematics with highest honors from UC Berkeley.

 

Dimitri Kusnezov

Under Secretary for Science & Technology
Department of Homeland Security

Dr. Dimitri Kusnezov [Kooz-NETS-off] was confirmed as the Under Secretary for the Science and Technology Directorate (S&T) on September 8, 2022. As the science advisor to the Homeland Security Secretary, Dr. Kusnezov heads the research, development, innovation and testing and evaluation activities in support of the Department of Homeland Security’s (DHS) operational Components and first responders across the nation. S&T is responsible for identifying operational gaps, conceptualizing art-of-the-possible solutions, and delivering operational results that improve the security and resilience of the nation. 

Prior to DHS, Dr. Kusnezov was a theoretical physicist working at the U.S. Department of Energy (DOE) focusing on emerging technologies. He served in numerous positions, including the Deputy Under Secretary for Artificial Intelligence (AI) & Technology where he led efforts to drive AI innovation and bring it into DOE missions, business and operations, including through the creation of a new AI Office. 

Dr. Kusnezov has served in scientific and national security positions, including Senior Advisor to the Secretary of Energy, Chief Scientist for the National Nuclear Security Administration, Director of Advanced Simulation and Computing and the Director of the multi-billion-dollar National Security Science, Technology and Engineering programs. He created numerous programs, including for Minority Serving Institutions, international partners, private sector and philanthropic entities. He has worked across agencies to deliver major milestones such as DOE’s 10-year grand challenge for a 100 Teraflop supercomputer, and first of their kind and world’s fastest supercomputers. 

Prior to DOE and his pursuit of public service, Dr. Kusnezov had a long career in academia where he published more than 100 articles and edited two books. He joined Yale University faculty where he was a professor for more than a decade in Theoretical Physics and served as a visiting professor at numerous universities around the world. Before this post, Dr. Kusnezov did a brief postdoc and was an instructor at Michigan State University, following a year of research at the Institut fur Kernphysik, KFA-Julich, in Germany. He earned his MS in Physics and Ph.D. in Theoretical Nuclear Physics at Princeton University and received Bachelor of Arts degrees in Physics and in Pure Mathematics with highest honors from UC Berkeley.

 

11:30 AM - 12:15 PM
FOUNDING PARTNER PANEL

CPU performance improvement based on Dennard scaling and Moore's Law has already reached its limit, and domain-specific computing was considered as an alternative to overcome the limitations of the existing CPU-centric computing model. Domain-specific computing, seen in early graphics and network cards, has expanded into accelerators such as GPGPUS, TPUs, FPGAS, and IDPs. Meanwhile, hyperscalers, where power efficiency is particularly important, use ASICs or FPGAs to offload and accelerate OS, security, and data processing tasks. Handling large amounts of data in a power-efficient manner requires reexamining the model for moving data from traditional storage to the CPU. This model consumes a lot of power and limits performance due to bandwidth limitations. Computer Storage (CS) or In-Storage Computing (ISC), first explored in the 1990s, is another important piece of the puzzle. As data is explosively generated in the cloud, machine learning, big data, and edge, the industry is actively reviewing the application of CS in various fields. This panel discusses the current state of CS, its potentials and challenges in various applications.

Emerging Memories
Embedded Memory
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Yang Seok Ki

CXL Board of Director, VP and CTO of Memory Solutions Lab
Samsung Electronics

Dr. Yang Seok Ki is a Vice President and CTO of the Memory Solutions Lab (MSL) at Samsung Semiconductor Inc. in San Jose, California. Since joining Samsung in 2011, he has led various advanced development projects including SmartSSD, Key-Value SSD, CXL Memory Expander, Memory Semantic SSD, etc. In addition, he led the NVMe Key Value Standard, SNIA Key Value API, SNIA Computational Storage Architecture and API. He is a CXL board of director and a technical chair of Data Centric Computing workstream of the Open Computing Project (OCP) Future Technology Initiative (FTI). Prior to joining Samsung, he worked for Oracle's Server Technology Group. Prior to his industrial career, he was involved in High Performance Computing (HPC), Grid Computing, and Cloud research at the Institute of Information Sciences at the University of Southern California and the Center for Networked Systems at the University of California, San Diego. He received his Ph.D. in Electrical Engineering and Computer Engineering from Seoul National University, and his Master's and Bachelor's degrees in Computer Engineering from Seoul National University. He also completed the Engineering Leadership Professional Program (ELPP) from the University of California, Berkeley.

Yang Seok Ki

CXL Board of Director, VP and CTO of Memory Solutions Lab
Samsung Electronics

Dr. Yang Seok Ki is a Vice President and CTO of the Memory Solutions Lab (MSL) at Samsung Semiconductor Inc. in San Jose, California. Since joining Samsung in 2011, he has led various advanced development projects including SmartSSD, Key-Value SSD, CXL Memory Expander, Memory Semantic SSD, etc. In addition, he led the NVMe Key Value Standard, SNIA Key Value API, SNIA Computational Storage Architecture and API. He is a CXL board of director and a technical chair of Data Centric Computing workstream of the Open Computing Project (OCP) Future Technology Initiative (FTI). Prior to joining Samsung, he worked for Oracle's Server Technology Group. Prior to his industrial career, he was involved in High Performance Computing (HPC), Grid Computing, and Cloud research at the Institute of Information Sciences at the University of Southern California and the Center for Networked Systems at the University of California, San Diego. He received his Ph.D. in Electrical Engineering and Computer Engineering from Seoul National University, and his Master's and Bachelor's degrees in Computer Engineering from Seoul National University. He also completed the Engineering Leadership Professional Program (ELPP) from the University of California, Berkeley.

Panellists

Author:

Stephen Bates

VP & Chief Architect, Emerging Storage Systems
Huawei

Stephen is the VP and  Chief Architect of Emerging Storage Systems at Huawei's Toronto Emerging Storage Lab. He and his team research all aspects of next-generation storage systems from media to programming interfaces to filesystems to virtualized storage to applications.

Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding. He is also very active in both the SNIA and NVM Express standard bodies.

Prior to Huawei he was the CTO of Eideticom which is a pioneer company in NVMe-based computational storage. He was also formerly in the CTO office at PMC-Sierra, an Assistant Professor at The Univeristy of Alberta and a Principal Engineer at Massana Inc. Stephen has a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

Stephen Bates

VP & Chief Architect, Emerging Storage Systems
Huawei

Stephen is the VP and  Chief Architect of Emerging Storage Systems at Huawei's Toronto Emerging Storage Lab. He and his team research all aspects of next-generation storage systems from media to programming interfaces to filesystems to virtualized storage to applications.

Stephen is an expert in performance storage, persistent and non-volatile memory, computer networking, signal processing and error correction coding. He is also very active in both the SNIA and NVM Express standard bodies.

Prior to Huawei he was the CTO of Eideticom which is a pioneer company in NVMe-based computational storage. He was also formerly in the CTO office at PMC-Sierra, an Assistant Professor at The Univeristy of Alberta and a Principal Engineer at Massana Inc. Stephen has a PhD from the University of Edinburgh and is a Senior Member of the IEEE.

Author:

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Author:

Seong Kim

Senior Director, Datacenter Solutions Architect
AMD

As the leader of the global data center solutions architect group at AMD, Seong is focused on driving the development of data center application acceleration and offload for compute, network, and storage solutions. Seong’s recent focuses are on smart video analytics, machine learning, database acceleration, smart NIC, smart SSD and computational storage accelerations.

 

Seong holds a Ph.D. in Electrical and Computer Engineering and an MBA in Marketing. He has authored numerous technical papers, white papers, and patents, and has presented industry seminars. Throughout his career, Seong has developed proof-of-concept solutions for data center, wireless, and wireline applications using network processors, FPGA, x86 & ARM, and networking peripherals. He is proactively recommending courses of action to bring competitiveness to the solutions and defining the roadmap and next-generation platforms.

Seong Kim

Senior Director, Datacenter Solutions Architect
AMD

As the leader of the global data center solutions architect group at AMD, Seong is focused on driving the development of data center application acceleration and offload for compute, network, and storage solutions. Seong’s recent focuses are on smart video analytics, machine learning, database acceleration, smart NIC, smart SSD and computational storage accelerations.

 

Seong holds a Ph.D. in Electrical and Computer Engineering and an MBA in Marketing. He has authored numerous technical papers, white papers, and patents, and has presented industry seminars. Throughout his career, Seong has developed proof-of-concept solutions for data center, wireless, and wireline applications using network processors, FPGA, x86 & ARM, and networking peripherals. He is proactively recommending courses of action to bring competitiveness to the solutions and defining the roadmap and next-generation platforms.

Author:

Keith McKay

Senior Director
ScaleFlux

Keith McKay

Senior Director
ScaleFlux

Author:

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

Author:

Jongryool Kim

Research Director
SK Hynix

Jongryool Kim is currently a research director overseeing next generation architecture enablement at SK hynix where his team’s main responsibilities are to research and to fast-prototype new data storage technologies such as computational memory and storage solutions. Prior to this role, he worked with various R&D teams at Samsung’s SW R&D Center.

In addition, he had served as the key engineer and development manager on the data analytics system of Samsung Cloud at Samsung Mobile division. He earned his Ph.D degree in Computer Engineering form GIST, South Korea.

Jongryool Kim

Research Director
SK Hynix

Jongryool Kim is currently a research director overseeing next generation architecture enablement at SK hynix where his team’s main responsibilities are to research and to fast-prototype new data storage technologies such as computational memory and storage solutions. Prior to this role, he worked with various R&D teams at Samsung’s SW R&D Center.

In addition, he had served as the key engineer and development manager on the data analytics system of Samsung Cloud at Samsung Mobile division. He earned his Ph.D degree in Computer Engineering form GIST, South Korea.

12:15 PM - 1:30 PM
LUNCH
1:30 PM - 2:15 PM
USE CASE PANEL: DATACENTER & HPC

Working back from the question,"what do future systems architectures need to look like?", this panel will investigate the current memory, bandwidth and latency bottlenecks in systems today, and compare and contrast datacenter and HPC examples. In discussing the characteristics, similarities, and differences between various server workloads and use cases, such as AIML co-design, acceleration of scientific workloads and others, this panel will attempt to establish context for why memory innovation is so important.


Emerging Memories
External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Rob Ober

Chief Platform Architect
NVIDIA

Rob is NVIDIA’s data center Chief Platform Architect, working with Hyperscalers to build GPU clusters for AI and Deep Learning, develop systems and platform architecture, and influence the HW and SW GPU roadmaps at NVIDIA. His interest in AI and DL was driven by its impact on computer science and computer architecture.

With more than 35 years experience, Rob was Senior Fellow of Enterprise Technology at SanDisk / FusionIO, Corporate Fellow and Chief Architect at LSI; Fellow and Architect at AMD; Chief Architect at Infineon; Manager of Technologies at Apple Computer, as well as designer of supercomputers, mainframes, and networks.

Rob has over 40 international patents in processor architecture, storage systems, SSDs, networks, wireless, power management, and mobile devices. He has developed architecture and implementation of CRAY, ARM, PowerPC, ARC, Sparc, TriCore and x86 processors.

Rob Ober

Chief Platform Architect
NVIDIA

Rob is NVIDIA’s data center Chief Platform Architect, working with Hyperscalers to build GPU clusters for AI and Deep Learning, develop systems and platform architecture, and influence the HW and SW GPU roadmaps at NVIDIA. His interest in AI and DL was driven by its impact on computer science and computer architecture.

With more than 35 years experience, Rob was Senior Fellow of Enterprise Technology at SanDisk / FusionIO, Corporate Fellow and Chief Architect at LSI; Fellow and Architect at AMD; Chief Architect at Infineon; Manager of Technologies at Apple Computer, as well as designer of supercomputers, mainframes, and networks.

Rob has over 40 international patents in processor architecture, storage systems, SSDs, networks, wireless, power management, and mobile devices. He has developed architecture and implementation of CRAY, ARM, PowerPC, ARC, Sparc, TriCore and x86 processors.

Author:

Nick Wright

Chief Architect & Head, Advanced Technology Group
NERSC

Nick Wright is the advanced technologies group lead and the NERSC chief architect. He focuses upon evaluating future technologies for potential application in scientific computing. He led the effort to optimize the architecture of the Perlmutter machine, the first NERSC platform designed to meet needs of both large scale simulation and data analysis from experimental facilities. Before moving to NERSC, he was a member of the Performance Modeling and Characterization (PMaC) group at the San Diego Supercomputing Center. He earned both his undergraduate and doctoral degrees in chemistry at the University of Durham in England.

Nick Wright

Chief Architect & Head, Advanced Technology Group
NERSC

Nick Wright is the advanced technologies group lead and the NERSC chief architect. He focuses upon evaluating future technologies for potential application in scientific computing. He led the effort to optimize the architecture of the Perlmutter machine, the first NERSC platform designed to meet needs of both large scale simulation and data analysis from experimental facilities. Before moving to NERSC, he was a member of the Performance Modeling and Characterization (PMaC) group at the San Diego Supercomputing Center. He earned both his undergraduate and doctoral degrees in chemistry at the University of Durham in England.

Author:

Zaid Kahn

GM, Cloud AI & Advanced Systems Engineering
Microsoft

Zaid is currently GM in Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.

Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.

Zaid Kahn

GM, Cloud AI & Advanced Systems Engineering
Microsoft

Zaid is currently GM in Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.

Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.

Author:

David Emberson

Senior Distinguished Technologist
HPE

David Emberson is Senior Distinguished Technologist for HPC System Architecture, where he is working on future memory system designs for HPE Cray systems. He began his career at MIT's Digital Systems Laboratory, where he built one of the first portable computers in 1975. He has held positions at Prime Computer, Megatest, Ametek Computer Research, and Sun Microsystems. At Sun, Mr. Emberson was a member of the SPARC architecture committee, managed the SparcStation 10 and SparcStation 20 programs, and was Senior Director at SunLabs. His consulting clients have included the Hypertransport Consortium, AMD, Intel, Atheros, PathScale, Qlogic and numerous startup companies.

At HPE he was Technical Director of HPE's PathForward program for the Department of Energy's Exascale Computing Program. His current research is in memory system design for HPC systems. He serves on the JEDEC J42.2 (HBM) committee and is a Senior Member of IEEE. Mr. Emberson has a B.S. in Electrical Engineering from MIT. He holds nineteen patents.

David Emberson

Senior Distinguished Technologist
HPE

David Emberson is Senior Distinguished Technologist for HPC System Architecture, where he is working on future memory system designs for HPE Cray systems. He began his career at MIT's Digital Systems Laboratory, where he built one of the first portable computers in 1975. He has held positions at Prime Computer, Megatest, Ametek Computer Research, and Sun Microsystems. At Sun, Mr. Emberson was a member of the SPARC architecture committee, managed the SparcStation 10 and SparcStation 20 programs, and was Senior Director at SunLabs. His consulting clients have included the Hypertransport Consortium, AMD, Intel, Atheros, PathScale, Qlogic and numerous startup companies.

At HPE he was Technical Director of HPE's PathForward program for the Department of Energy's Exascale Computing Program. His current research is in memory system design for HPC systems. He serves on the JEDEC J42.2 (HBM) committee and is a Senior Member of IEEE. Mr. Emberson has a B.S. in Electrical Engineering from MIT. He holds nineteen patents.

Author:

Uri Rosenberg

Specialist Technical Manager, AI/ML
Amazon Web Services

Uri Rosenberg is the Specialist Technical Manager of AI & ML services within enterprise support at Amazon Web Services (AWS) EMEA. Uri works to empower enterprise customers on all things ML: from underwater computer vision models that monitor fish to training models on satellite images in space; from optimizing costs to strategic discussions on deep learning and ethics. Uri brings his extensive experience to drive success of customers at all stages of ML adoption.

Before AWS, Uri led the ML projects at AT&T innovation center in Israel, working on deep learning models with extreme security and privacy constraints.

Uri is also an AWS certified Lead Machine learning subject matter expert and holds an MsC in Computer Science from Tel-Aviv Academic College, where his research focused on large scale deep learning models.

Uri Rosenberg

Specialist Technical Manager, AI/ML
Amazon Web Services

Uri Rosenberg is the Specialist Technical Manager of AI & ML services within enterprise support at Amazon Web Services (AWS) EMEA. Uri works to empower enterprise customers on all things ML: from underwater computer vision models that monitor fish to training models on satellite images in space; from optimizing costs to strategic discussions on deep learning and ethics. Uri brings his extensive experience to drive success of customers at all stages of ML adoption.

Before AWS, Uri led the ML projects at AT&T innovation center in Israel, working on deep learning models with extreme security and privacy constraints.

Uri is also an AWS certified Lead Machine learning subject matter expert and holds an MsC in Computer Science from Tel-Aviv Academic College, where his research focused on large scale deep learning models.

2:15 PM - 2:40 PM
USE CASE: IN-MEMORY DATABASES

With current trends in DRAM capacities and costs, in-memory database technology is rapidly becoming mainstream. Oracle Database In-Memory features a unique dual-format in-memory architecture designed to optimize the performance of simultaneous analytic and transactional workloads on the same data. In addition, the in-memory columnar technology for Oracle Database In-Memory is also available within the storage tier of the Exadata database machine, allowing for effective in-memory columnar capacities to approach 100s of Terabytes.  In-memory processing is more than simply about speed; it enables a fundamental transformation in business processes. Just as air travel enabled more than faster travel - it fundamentally changed society, Oracle Database In-Memory similarly enables not just faster analytics and transactions, but a fundamental rethinking and drastic simplification of the traditional analytic architectures. In this session we will show how, especially when combined with Oracle's many converged database capabilities, Database In-Memory allows for the development of a new class of real-time enterprise applications, with significant reduction in cost and complexity, while providing unmatched performance across a wide range of workloads.

Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Tirthankar Lahiri

SVP, Data & In-Memory Technologies
Oracle

Tirthankar Lahiri is Vice President of the Data and In-Memory Technologies group for Oracle Database and is responsible for the Oracle Database Engine (including Database In-Memory, Data and Indexes, Space Management, Transactions, and the Database File System), the Oracle TimesTen In-Memory Database, and Oracle NoSQLDB. Tirthankar has 22 years of experience in the Database industry and has worked extensively in a variety of areas including Manageability, Performance, Scalability, High Availability, Caching, Distributed Concurrency Control, In-Memory Data Management, NoSQL architectures, etc. He has 27 issued and has several pending patents in these areas. Tirthankar has a B.Tech in Computer Science from the Indian Institute of Technology (Kharagpur) and an MS in Electrical Engineering from Stanford University.

Tirthankar Lahiri

SVP, Data & In-Memory Technologies
Oracle

Tirthankar Lahiri is Vice President of the Data and In-Memory Technologies group for Oracle Database and is responsible for the Oracle Database Engine (including Database In-Memory, Data and Indexes, Space Management, Transactions, and the Database File System), the Oracle TimesTen In-Memory Database, and Oracle NoSQLDB. Tirthankar has 22 years of experience in the Database industry and has worked extensively in a variety of areas including Manageability, Performance, Scalability, High Availability, Caching, Distributed Concurrency Control, In-Memory Data Management, NoSQL architectures, etc. He has 27 issued and has several pending patents in these areas. Tirthankar has a B.Tech in Computer Science from the Indian Institute of Technology (Kharagpur) and an MS in Electrical Engineering from Stanford University.

2:40 PM - 3:05 PM
USE CASE: GENOMICS

As the cost of sequencing drops and the quantity of data produced by sequencing grows, the amount of processing dedicated to genomics is increasing at a rapid pace.  Genomics is evolving in a number of directions simultaneously.  Some key applications scale naturally to use resources available in the cloud, while other computations benefit from on-prem acceleration using FPGAs or GPUs.  All of these computations strain the bandwidth and capacity of available resources.  In this talk, Roche´s Tom Sheffler will share an overview of the memory-bound challenges present in genomics and venture some possible solutions.

External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Tom Sheffler

Solution Architect, Next Generation Sequencing
Roche

Tom earned his PhD from Carnegie Mellon in Computer Engineering with a focus on parallel computing architectures and prrogramming models.  His interest in high-performance computing took him to NASA Ames, and then to Rambus where he worked on accelerated memory interfaces for providing high bandwidth.  Following that, he co-founded the cloud video analytics company, Sensr.net, that applied scalable cloud computing to analyzing large streams of video data.  He later joined Roche to work on next-generation sequencing and scalable genomics analysis platforms.  Throughout his career, Tom has focused on the application of high performance computer systems to real world problems.

Tom Sheffler

Solution Architect, Next Generation Sequencing
Roche

Tom earned his PhD from Carnegie Mellon in Computer Engineering with a focus on parallel computing architectures and prrogramming models.  His interest in high-performance computing took him to NASA Ames, and then to Rambus where he worked on accelerated memory interfaces for providing high bandwidth.  Following that, he co-founded the cloud video analytics company, Sensr.net, that applied scalable cloud computing to analyzing large streams of video data.  He later joined Roche to work on next-generation sequencing and scalable genomics analysis platforms.  Throughout his career, Tom has focused on the application of high performance computer systems to real world problems.

3:05 PM - 3:30 PM
USE CASE: ENTERPRISE KNOWLEDGE GRAPHS (EKGs)

Enterprise knowledge graphs (EKGs) offer the ability to store large connected datasets in memory for fast traversal using simple pointer-hopping instructions.  However, keeping hundreds or thousands of cores feed with traversal data has become one of the key challenges for artificial intelligence and analytics.  Despite the exponential growth in graphs databases we have yet to see hardware tuned to graph analytics workloads.  In this session we will review the requirements for EKGs and provide a roadmap of how new memory hardware can be used to solve EKG challenges.

Embedded Memory
External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Dan McCreary

Distinguished Engineer, Graph & AI
Optum

Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.

Dan McCreary

Distinguished Engineer, Graph & AI
Optum

Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.

3:30 PM - 4:00 PM
NETWORKING BREAK
4:00 PM - 4:25 PM
USE CASE: COMPUTATIONAL FLUID DYNAMICS

Recent work by the National Energy Technology Laboratory and Cerebras Systems Inc, has underscored the critical needs of sufficient bandwidth and latency in scientific computing.  In this work, the team demonstrated (to the best of our knowledge) the fastest solution to field equations in computing history.  These remarkable results were made possible by the trifecta of great memory bandwidth, great interconnect bandwidth, and amazing (one clock cycle) communication latency and injection rate for small messages.  Furthermore, the bandwidths are sufficiently high such that no memory hierarchy is necessary which significantly simplifies programming models and software development effort and expense.  In this talk we will outline the conditions necessary to achieve these results.

Embedded Memory
External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Dirk Van Essendelft

HPC & AI Architect
National Energy Technology Laboratory

Dr. Van Essendelft is the principle investigator for the integration of AI/ML with scientific simulations within in the Computational Device Engineering Team at the National Energy Technology Laboratory.  The focus of Dr. Van Essendelft’s work is building a comprehensive hardware and software ecosystem that maximizes speed, accuracy, and energy efficiency of AI/ML accelerated scientific simulations.  Currently, his work centers around building Computational Fluid Dynamics capability within the TensorFlow framework, generating AI/ML based predictors, and ensuring the ecosystem is compatible with the fastest possible accelerators and processors in industry.  In this way, Dr. Van Essendelft is developing NETL’s first cognitive-in-the-loop simulation capability in which AI/ML models can be used any point to bring acceleration and/or closures in new ways.  Dr. Van Essendelft sits on the Technical Advisory Group for NETL’s new Science-Based Artificial Intelligence/Machine Learning Institute (SAMI) and holds degrees in Energy and Geo-Environmental Engineering, Chemical and Biochemical Engineering, and Chemical Engineering from the Pennsylvania State University, University of California, Irvine, and Calvin College respectively.

Recent publications:

  • Rocki, K., Van Essendelft, D., Sharapov, I., Schreiber, R., Morrison, M., Kibardin, V., Portnoy, A., Dietiker, J. F., Syamlal, M., and James, M. (2020) Fast stencil-code computation on a wafer-scale processor, In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp pp 1-14, IEEE Press, Atlanta, Georgia.

Dirk Van Essendelft

HPC & AI Architect
National Energy Technology Laboratory

Dr. Van Essendelft is the principle investigator for the integration of AI/ML with scientific simulations within in the Computational Device Engineering Team at the National Energy Technology Laboratory.  The focus of Dr. Van Essendelft’s work is building a comprehensive hardware and software ecosystem that maximizes speed, accuracy, and energy efficiency of AI/ML accelerated scientific simulations.  Currently, his work centers around building Computational Fluid Dynamics capability within the TensorFlow framework, generating AI/ML based predictors, and ensuring the ecosystem is compatible with the fastest possible accelerators and processors in industry.  In this way, Dr. Van Essendelft is developing NETL’s first cognitive-in-the-loop simulation capability in which AI/ML models can be used any point to bring acceleration and/or closures in new ways.  Dr. Van Essendelft sits on the Technical Advisory Group for NETL’s new Science-Based Artificial Intelligence/Machine Learning Institute (SAMI) and holds degrees in Energy and Geo-Environmental Engineering, Chemical and Biochemical Engineering, and Chemical Engineering from the Pennsylvania State University, University of California, Irvine, and Calvin College respectively.

Recent publications:

  • Rocki, K., Van Essendelft, D., Sharapov, I., Schreiber, R., Morrison, M., Kibardin, V., Portnoy, A., Dietiker, J. F., Syamlal, M., and James, M. (2020) Fast stencil-code computation on a wafer-scale processor, In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp pp 1-14, IEEE Press, Atlanta, Georgia.

4:25 PM - 4:50 PM
PRESENTATION

High-throughput, low latency data movement between compute resources (memory included) has become a bottleneck in modern distributed computing workloads such as AI/ML, HPC, and databases. The interconnect fabrics for the two main types of data movement in compute - load store memory access and byte moving I/O - have historically been built and treated disparately. While this made sense when CPU I/O and network interfaces were far lower bandwidth than memory interfaces, their interconnect is now at an architectural merge point. In this keynote, Enfabrica will reveal its blueprint for any-scale, high-bandwidth, latency-tiered memory movement in the data center based on fabrics that blend load store and local DMA primitives (over CXL, PCIe, and similar) with RDMA over network technologies running at 800 Gbps and beyond. We will highlight the efficiencies of such a unified fabric architecture, its ability to render high-throughput memory movement as scalable and hierarchical from chipset to cluster, and its utility as an infrastructure building block that fits seamlessly within existing, robust system software frameworks.

Embedded Memory
Emerging Memories
External Memory
Use Case
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Shrijeet Mukherjee

Co-Founder & Chief Development Officer
Enfabrica

Shrijeet is a Co-Founder and the Chief Development Officer of Enfabrica. Prior to founding Enfabrica, he was an architect in Google’s infrastructure group. Previously, he was VP Engineering at Cumulus Networks where he built the industry’s first disaggregated Linux-native network operating system. He was the software engineering leader and architect of the industry’s first virtualization/storage offload “smart-NICs” for Cisco UCS. At SGI he was part of the Advanced Graphics team that pioneered floating point framebuffers and programmable shaders. Shrijeet is on the Linux NetDev Society Board of Directors and has over 20 patents. He holds an MS in Computer Science from the University of Oregon.

Shrijeet Mukherjee

Co-Founder & Chief Development Officer
Enfabrica

Shrijeet is a Co-Founder and the Chief Development Officer of Enfabrica. Prior to founding Enfabrica, he was an architect in Google’s infrastructure group. Previously, he was VP Engineering at Cumulus Networks where he built the industry’s first disaggregated Linux-native network operating system. He was the software engineering leader and architect of the industry’s first virtualization/storage offload “smart-NICs” for Cisco UCS. At SGI he was part of the Advanced Graphics team that pioneered floating point framebuffers and programmable shaders. Shrijeet is on the Linux NetDev Society Board of Directors and has over 20 patents. He holds an MS in Computer Science from the University of Oregon.

4:50 PM - 5:20 PM
USE CASE PANEL: AIML

The AI ´memory wall´is well documented, where AIML applications are hitting bottlenecks in intra/inter-chip and communication across/to AIML accelerators. Memory requirements to train AIML models are typically several times larger than the number of parameters, while the speed of data transfer has consistently failed to keep up with advancements in compute capabilities.

In the innovative world of dedicated AIML processors and systems, there have been a variety of approaches, both at the chip and systems level, to engineering around these challenges. This panel will look at how leading engineering teams working in this space are tackling the AI memory wall and how they see requirements shifting as requirements for new types of models evolve.

Embedded Memory
Emerging Memories
External Memory
Systems Design
Use Case
Hardware Eng.
Memory Systems Eng.
Systems Architecture
Moderator

Author:

Jean Bozman

President
Cloud Architects Advisors, LLC

Jean S. Bozman is an IT industry analyst focusing on cloud infrastructure and the proud founder of a new company, Cloud Architects Advisors LLC.

She has had experience as an IDC Research VP for 10+ years and has covered the semiconductor industry as an analyst for over 20 years.

Jean Bozman

President
Cloud Architects Advisors, LLC

Jean S. Bozman is an IT industry analyst focusing on cloud infrastructure and the proud founder of a new company, Cloud Architects Advisors LLC.

She has had experience as an IDC Research VP for 10+ years and has covered the semiconductor industry as an analyst for over 20 years.

Panellists

Author:

Sumti Jairath

Chief Architect
SambaNova Systems

Sumti Jairath is Chief Architect at SambaNova Systems, with expertise in hardware-software co-design. Sumti worked on PA-RISC-based Superdome servers back at HP, followed by several generations of SPARC CMT processors at Sun Microsystems and Oracle. At Oracle, Sumti worked on SQL, Data-analytics and Machine Learning acceleration in SPARC processors. Sumti holds 27 patents in computer architecture and hardware-software co-design.

 

Sumti Jairath

Chief Architect
SambaNova Systems

Sumti Jairath is Chief Architect at SambaNova Systems, with expertise in hardware-software co-design. Sumti worked on PA-RISC-based Superdome servers back at HP, followed by several generations of SPARC CMT processors at Sun Microsystems and Oracle. At Oracle, Sumti worked on SQL, Data-analytics and Machine Learning acceleration in SPARC processors. Sumti holds 27 patents in computer architecture and hardware-software co-design.

 

Author:

Venkatram Vishwanath

Data Science Team Lead
Argonne National Laboratory

Venkatram Vishwanath is a computer scientist at Argonne National Laboratory. He is the Data Science Team Lead at the Argonne leadership computing facility (ALCF). His current focus is on algorithms, system software, and workflows to facilitate data-centric applications on supercomputing systems. His interests include scientific applications, supercomputing architectures, parallel algorithms and runtimes, scalable analytics and collaborative workspaces. He has received best papers awards at venues including HPDC and LDAV, and a Gordon Bell finalist. Vishwanath received his Ph.D. in computer science from the University of Illinois at Chicago in 2009.

Research Interests

  • Scientific data analysis and visualization
  • Parallel I/O and I/O middleware
  • Large-scale computing systems and other exotic architectures (Blue Gene, Cray, multi-core systems, GPUs and other accelerators)
  • High-speed interconnects (InfiniBand, high-speed Ethernet, optical), data movement and transfer protocols, and (v) collaboration workspaces

 

Venkatram Vishwanath

Data Science Team Lead
Argonne National Laboratory

Venkatram Vishwanath is a computer scientist at Argonne National Laboratory. He is the Data Science Team Lead at the Argonne leadership computing facility (ALCF). His current focus is on algorithms, system software, and workflows to facilitate data-centric applications on supercomputing systems. His interests include scientific applications, supercomputing architectures, parallel algorithms and runtimes, scalable analytics and collaborative workspaces. He has received best papers awards at venues including HPDC and LDAV, and a Gordon Bell finalist. Vishwanath received his Ph.D. in computer science from the University of Illinois at Chicago in 2009.

Research Interests

  • Scientific data analysis and visualization
  • Parallel I/O and I/O middleware
  • Large-scale computing systems and other exotic architectures (Blue Gene, Cray, multi-core systems, GPUs and other accelerators)
  • High-speed interconnects (InfiniBand, high-speed Ethernet, optical), data movement and transfer protocols, and (v) collaboration workspaces

 

5:20 PM - 6:05 PM
PANEL
Embedded Memory
Emerging Memories
Hardware Eng.
Memory Systems Eng.
Moderator

Author:

Jim Handy

General Director
Objective Analysis

Jim Handy of Objective Analysis has over 35 years in the electronics industry including 20 years as a leading semiconductor and SSD industry analyst. Early in his career he held marketing and design positions at leading semiconductor suppliers including Intel, National Semiconductor, and Infineon. A frequent presenter at trade shows, Mr. Handy is highly respected for his technical depth, accurate forecasts, widespread industry presence and volume of publication. He has written hundreds of market reports, articles for trade journals, and white papers, and is frequently interviewed and quoted in the electronics trade press and other media.

Jim Handy

General Director
Objective Analysis

Jim Handy of Objective Analysis has over 35 years in the electronics industry including 20 years as a leading semiconductor and SSD industry analyst. Early in his career he held marketing and design positions at leading semiconductor suppliers including Intel, National Semiconductor, and Infineon. A frequent presenter at trade shows, Mr. Handy is highly respected for his technical depth, accurate forecasts, widespread industry presence and volume of publication. He has written hundreds of market reports, articles for trade journals, and white papers, and is frequently interviewed and quoted in the electronics trade press and other media.

Panellists

Author:

Tirthankar Lahiri

SVP, Data & In-Memory Technologies
Oracle

Tirthankar Lahiri is Vice President of the Data and In-Memory Technologies group for Oracle Database and is responsible for the Oracle Database Engine (including Database In-Memory, Data and Indexes, Space Management, Transactions, and the Database File System), the Oracle TimesTen In-Memory Database, and Oracle NoSQLDB. Tirthankar has 22 years of experience in the Database industry and has worked extensively in a variety of areas including Manageability, Performance, Scalability, High Availability, Caching, Distributed Concurrency Control, In-Memory Data Management, NoSQL architectures, etc. He has 27 issued and has several pending patents in these areas. Tirthankar has a B.Tech in Computer Science from the Indian Institute of Technology (Kharagpur) and an MS in Electrical Engineering from Stanford University.

Tirthankar Lahiri

SVP, Data & In-Memory Technologies
Oracle

Tirthankar Lahiri is Vice President of the Data and In-Memory Technologies group for Oracle Database and is responsible for the Oracle Database Engine (including Database In-Memory, Data and Indexes, Space Management, Transactions, and the Database File System), the Oracle TimesTen In-Memory Database, and Oracle NoSQLDB. Tirthankar has 22 years of experience in the Database industry and has worked extensively in a variety of areas including Manageability, Performance, Scalability, High Availability, Caching, Distributed Concurrency Control, In-Memory Data Management, NoSQL architectures, etc. He has 27 issued and has several pending patents in these areas. Tirthankar has a B.Tech in Computer Science from the Indian Institute of Technology (Kharagpur) and an MS in Electrical Engineering from Stanford University.

Author:

Pedram Khalili

Associate Professor of Electrical and Computer Engineering
Northwestern University

Pedram Khalili-Amiri works on developing the computing systems of the future, starting from novel nano-scale devices/materials that enable systems with unprecedented performance and energy efficiency. Much of his work involves devices that use both the spin and charge of electrons, also referred to as spintronics. Previously Pedram was an adjunct assistant professor in the department of electrical and computer engineering at UCLA from 2013-2017, where he co-led the memory program within the NSF TANMS center, focusing on development of electric-field-controlled magnetic memory with unprecedented energy efficiency. During 2009-2014, at UCLA he was project manager of two DARPA multi-institution programs, focusing on the development of spin-transfer-torque magnetic random access memory (STT-MRAM) and non-volatile logic (NVL), working with several major industry and university partners. These programs resulted in the world’s fastest and lowest-power magnetic memory technologies at the time. In addition, since 2012 he has been co-founder of Inston Inc., a startup company pioneering voltage-controlled MRAM for high-performance computing applications, where he also served as board member and chief technology officer  for five years. His professional activities have included serving as a guest editor for Spin, and serving on the technical program committee of the Joint MMM/Intermag Conference.

Pedram Khalili

Associate Professor of Electrical and Computer Engineering
Northwestern University

Pedram Khalili-Amiri works on developing the computing systems of the future, starting from novel nano-scale devices/materials that enable systems with unprecedented performance and energy efficiency. Much of his work involves devices that use both the spin and charge of electrons, also referred to as spintronics. Previously Pedram was an adjunct assistant professor in the department of electrical and computer engineering at UCLA from 2013-2017, where he co-led the memory program within the NSF TANMS center, focusing on development of electric-field-controlled magnetic memory with unprecedented energy efficiency. During 2009-2014, at UCLA he was project manager of two DARPA multi-institution programs, focusing on the development of spin-transfer-torque magnetic random access memory (STT-MRAM) and non-volatile logic (NVL), working with several major industry and university partners. These programs resulted in the world’s fastest and lowest-power magnetic memory technologies at the time. In addition, since 2012 he has been co-founder of Inston Inc., a startup company pioneering voltage-controlled MRAM for high-performance computing applications, where he also served as board member and chief technology officer  for five years. His professional activities have included serving as a guest editor for Spin, and serving on the technical program committee of the Joint MMM/Intermag Conference.

Author:

Simone Bertolazzi

Senior Technology & Market Analyst
Yole Group

Simone Bertolazzi, PhD is a Senior Technology & Market analyst, Memory, at Yole Intelligence, part of Yole Group, working with the Semiconductor, Memory & Computing division. As member of the Yole’s memory team, he contributes on a day-to-day basis to the analysis of memory markets and technologies, their related materials, device architectures and fabrication processes. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland) and a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.

Simone Bertolazzi

Senior Technology & Market Analyst
Yole Group

Simone Bertolazzi, PhD is a Senior Technology & Market analyst, Memory, at Yole Intelligence, part of Yole Group, working with the Semiconductor, Memory & Computing division. As member of the Yole’s memory team, he contributes on a day-to-day basis to the analysis of memory markets and technologies, their related materials, device architectures and fabrication processes. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland) and a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.

6:05 PM - 7:00 PM
DRINKS RECEPTION
Wednesday, 29 Mar, 2023
09:30 AM
REGISTRATION AND EXHIBITS OPEN
10:00 AM - 10:30 AM
OPENING KEYNOTE
10:30 AM - 11:00 AM
KEYNOTE

The leading companies at every level of the data center value chain, from IP, chips, platforms, system OEMs to hyperscalers, are coalescing around CXL technology as a path to revolutionize the data center. With workload demands increasing rapidly, the need for more memory bandwidth and capacity continues to rise. Memory is of critical importance, and its share of the server bill of materials (BoM) continues to grow. Making the best use of vital memory resources is an imperative. With CXL technology, the industry is pursuing tiered-memory solutions that can break through the memory bottleneck while at the same time delivering greater efficiency and improved TCO. Ultimately, CXL technology can support composable architectures that match the amount of compute, memory and storage in an on-demand fashion to the needs of a wide range of advanced workloads.    

CXL
Embedded Memory
Emerging Memories
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Mark Orthodoxou

VP, Strategic Marketing, Datacenter Product
Rambus

Mark Orthodoxou is the Vice President of Strategic Marketing for Rambus’ Datacenter Products Group. Mark has over 25 years of experience in product management and strategic planning in the semiconductor industry across multiple technology disciplines, including enterprise storage, data center compute, memory subsystems and networking. Mark has evangelized the benefits of serial-attached memory since long before CXL was introduced as a standard and was responsible for the introduction of the first commercially available products in this space. Mark currently sits on the CXL Consortium Marketing Working Group. He has held various leadership positions at Microchip, Microsemi, PMC-Sierra, and IDT.

Mark Orthodoxou

VP, Strategic Marketing, Datacenter Product
Rambus

Mark Orthodoxou is the Vice President of Strategic Marketing for Rambus’ Datacenter Products Group. Mark has over 25 years of experience in product management and strategic planning in the semiconductor industry across multiple technology disciplines, including enterprise storage, data center compute, memory subsystems and networking. Mark has evangelized the benefits of serial-attached memory since long before CXL was introduced as a standard and was responsible for the introduction of the first commercially available products in this space. Mark currently sits on the CXL Consortium Marketing Working Group. He has held various leadership positions at Microchip, Microsemi, PMC-Sierra, and IDT.

11:00 AM - 11:30 AM
KEYNOTE

Over the last two decades, large HPC machine efforts have become a procurement exercise.  A large set of applications have been unable to leverage the additional computational power of newly-procured machines without significant additional software development.  The machine architectures need to evolve:  new systems architectures and innovations require a deep understanding of application uses cases and their needs.   Memory and storage, as foundational elements, will be at the center of future innovative systems, driving both greater performance and increased energy efficiency.

CXL
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture

Author:

Steve Pawlowski

CVP, Advanced Memory Systems
Micron

Steve Pawlowski is corporate vice president of advanced computing solutions at Micron Technology. He is responsible for defining and developing innovative memory solutions for the enterprise and high performance computing markets.

Prior to joining Micron in July 2014, Steve was a senior fellow and the chief technology officer for Intel’s Data Center and Connected Systems Group. His extensive industry experience includes 31 years at Intel, where he held several high-level positions and led teams in the design and development of next-generation system architectures and computing platforms.

Steve earned bachelor’s degrees in electrical engineering and computer systems engineering technology from the Oregon Institute of Technology and a master’s degree in computer science and engineering from the Oregon Graduate Institute. He also holds 58 patents.

Steve Pawlowski

CVP, Advanced Memory Systems
Micron

Steve Pawlowski is corporate vice president of advanced computing solutions at Micron Technology. He is responsible for defining and developing innovative memory solutions for the enterprise and high performance computing markets.

Prior to joining Micron in July 2014, Steve was a senior fellow and the chief technology officer for Intel’s Data Center and Connected Systems Group. His extensive industry experience includes 31 years at Intel, where he held several high-level positions and led teams in the design and development of next-generation system architectures and computing platforms.

Steve earned bachelor’s degrees in electrical engineering and computer systems engineering technology from the Oregon Institute of Technology and a master’s degree in computer science and engineering from the Oregon Graduate Institute. He also holds 58 patents.

11:30 AM - 12:00 PM
PRESENTATION
CXL
Embedded Memory
Emerging Memories
External Memory
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

12:00 PM - 1:00 PM
LUNCH
1:00 PM - 1:45 PM
FOUNDING PARTNER PANEL

Standard computer architectures suffer from von Neumann bottlenecks for all processing is done exclusively on the processor.
The computer's memory is not involved in processing, as it is only used to store programs and data. When a computing system or application has large amounts of data, moving data between memory and the processor can slow down processing.
Adding processing directly into memory can help alleviate this problem. Processing In Memory (PIM) or Processing Near Memory (PNM) is capable of manipulating data in computer memory.
By moving part of the computation to a memory device, PIM/PNM solves a fundamental problem in modern computing system design: the mismatch between von Neumann architectures and the huge memory bandwidth demanding of applications.
Many industrial prototypes and products are under development or are already available on the market, and these devices show promise for cost-effective and energy-efficient acceleration of HPC, AI, and Big-Data analytics workloads.
This panel will discuss the reasons for the renewed interest in PIM/PNM and its technological readiness and challenges in terms of Applications, System and SW.

Embedded Memory
Emerging Memories
Hardware Eng.
Memory Systems Eng.
Moderator

Author:

Seungwon Lee

VP of Technology (Master), Samsung Advanced Institute of Technology
Samsung Electronics

Seungwon Lee is a Master (VP of Technology) at Samsung, where he leads Computing SW Team at SAIT(Samsung Advanced Institute of Technology) of Samsung Electronics.

His research interests include large scale deep learning computing SW and In/Near memory computing SW.

Lee received a Ph.D degree in computer science and engineering from Seoul National University.

Seungwon Lee

VP of Technology (Master), Samsung Advanced Institute of Technology
Samsung Electronics

Seungwon Lee is a Master (VP of Technology) at Samsung, where he leads Computing SW Team at SAIT(Samsung Advanced Institute of Technology) of Samsung Electronics.

His research interests include large scale deep learning computing SW and In/Near memory computing SW.

Lee received a Ph.D degree in computer science and engineering from Seoul National University.

Panellists

Author:

George Apostol

Founder & CEO
Elastics.cloud

George has over 35 years of experience designing system-on-chip (SoC), hardware, software, and systems. He holds several patents for interconnect and interface design and has led technology organizations developing products for several markets. He has held leadership and executive roles at Xerox/PARC, Sun, SGI, LSI Logic, Exar, and Samsung as well as start-ups including TiVo, BRECIS, Audience and BAYIS. As VP of Engineering and CTO at PLX Technology, George drove the development of  PCI Express switches, which are broadly used in the market today. He received his bachelor’s degree in Electrical Engineering from the Massachusetts Institute of Technology.

George Apostol

Founder & CEO
Elastics.cloud

George has over 35 years of experience designing system-on-chip (SoC), hardware, software, and systems. He holds several patents for interconnect and interface design and has led technology organizations developing products for several markets. He has held leadership and executive roles at Xerox/PARC, Sun, SGI, LSI Logic, Exar, and Samsung as well as start-ups including TiVo, BRECIS, Audience and BAYIS. As VP of Engineering and CTO at PLX Technology, George drove the development of  PCI Express switches, which are broadly used in the market today. He received his bachelor’s degree in Electrical Engineering from the Massachusetts Institute of Technology.

Author:

Andy Mills

Senior Director, Advanced Product Development
SMART Modular Technologies

Andy Mills is the Snr Director of Advanced Product Development at SMART Modular Technologies, where he leads the development of next generation CXL memory and data center storage solutions.

 

Prior to joining SMART, Andy was CEO/co-founder of Enmotus, Inc where he co-developed and led the development of intelligent storage and memory tiering solutions for data center and high end PCs utilizing advanced learning algorithms driven by real time intelligent workload analysis. He has more than 30 years industry experience in software development, systems architecture, networking, storage and semiconductor development, plus held various management and technical lead positions at DotHill Systems, NetCell Corporation, TDK Semi, AMD.

 

Andy graduated with an MEng and BEng with Honors from Bangor University in the UK.

Andy Mills

Senior Director, Advanced Product Development
SMART Modular Technologies

Andy Mills is the Snr Director of Advanced Product Development at SMART Modular Technologies, where he leads the development of next generation CXL memory and data center storage solutions.

 

Prior to joining SMART, Andy was CEO/co-founder of Enmotus, Inc where he co-developed and led the development of intelligent storage and memory tiering solutions for data center and high end PCs utilizing advanced learning algorithms driven by real time intelligent workload analysis. He has more than 30 years industry experience in software development, systems architecture, networking, storage and semiconductor development, plus held various management and technical lead positions at DotHill Systems, NetCell Corporation, TDK Semi, AMD.

 

Andy graduated with an MEng and BEng with Honors from Bangor University in the UK.

Author:

Seyong Lee

Senior R&D Staff
Oak Ridge National Laboratory

Seyong Lee is a Senior R&D Staff in the Computer Science and Mathematics Division at Oak Ridge National Laboratory (ORNL). His research interests include parallel programming and performance optimization in heterogeneous computing environments, program analysis, and optimizing compilers. He received his PhD in Electrical and Computer Engineering from Purdue University, USA.

He is a member of the OpenACC Technical Committee and a former member of the Seed Review Committee of the ORNL Seed Program and the NVIDIA PathForward Working Group of the Exascale Computing Project PathForward Program.

He served as a program committee/guest editor/external reviewer for various conferences, journals, and research proposals.

His paper on SC10 won the best student paper award, and his paper on PPoPP09 was selected as the most cited paper among all papers published in PPoPP between 2009 and 2014.

He received the IEEE Computer Society TCHPC Award for Excellence for Early Career Researchers in High Performance Computing at SC16 and served as an award committee member for 2017 IEEE CS TCHPC Award. 

See his website for more information: https://seyonglee.github.io.

Seyong Lee

Senior R&D Staff
Oak Ridge National Laboratory

Seyong Lee is a Senior R&D Staff in the Computer Science and Mathematics Division at Oak Ridge National Laboratory (ORNL). His research interests include parallel programming and performance optimization in heterogeneous computing environments, program analysis, and optimizing compilers. He received his PhD in Electrical and Computer Engineering from Purdue University, USA.

He is a member of the OpenACC Technical Committee and a former member of the Seed Review Committee of the ORNL Seed Program and the NVIDIA PathForward Working Group of the Exascale Computing Project PathForward Program.

He served as a program committee/guest editor/external reviewer for various conferences, journals, and research proposals.

His paper on SC10 won the best student paper award, and his paper on PPoPP09 was selected as the most cited paper among all papers published in PPoPP between 2009 and 2014.

He received the IEEE Computer Society TCHPC Award for Excellence for Early Career Researchers in High Performance Computing at SC16 and served as an award committee member for 2017 IEEE CS TCHPC Award. 

See his website for more information: https://seyonglee.github.io.

Author:

Nuwan Jayasena

Fellow
AMD

Nuwan Jayasena is a Fellow at AMD Research, and leads a team exploring hardware support, software enablement, and application adaptation for processing in memory. His broader interests include memory system architecture, accelerator-based computing, and machine learning. Nuwan holds an M.S. and a Ph.D. in Electrical Engineering from Stanford University and a B.S. from the University of Southern California. He is an inventor of over 70 US patents, an author of over 30 peer-reviewed publications, and a Senior Member of the IEEE. Prior to AMD, Nuwan was a processor architect at Nvidia Corp. and at Stream Processors, Inc.

Nuwan Jayasena

Fellow
AMD

Nuwan Jayasena is a Fellow at AMD Research, and leads a team exploring hardware support, software enablement, and application adaptation for processing in memory. His broader interests include memory system architecture, accelerator-based computing, and machine learning. Nuwan holds an M.S. and a Ph.D. in Electrical Engineering from Stanford University and a B.S. from the University of Southern California. He is an inventor of over 70 US patents, an author of over 30 peer-reviewed publications, and a Senior Member of the IEEE. Prior to AMD, Nuwan was a processor architect at Nvidia Corp. and at Stream Processors, Inc.

Author:

Paul Crumley

Senior Technical Staff Member
IBM Research

Paul G Crumley, a Senior Technical Staff Member at IBM Research, enjoys creating systems to solve problems beyond the reach of current technology.

 

Paul’s current project integrates secure, compliant AI capabilities with enterprise Hybrid Cloud allowing clients to extract new business value from their data.

 

Paul’s previous work includes the design and construction of distributed, and high-performance computing systems at CMU, Transarc, and IBM Research. Projects include The Andrew Project at CMU, ASCI White, IBM Global Storage Architecture, Blue Gene Supercomputers, IBM Cloud, and IBM Cognitive Systems. Paul has managed data centers, and brings his first-hand knowledge of these environments, combined with experience of automation and robustness, to the design of AI for Hybrid Cloud infrastructure.

Paul Crumley

Senior Technical Staff Member
IBM Research

Paul G Crumley, a Senior Technical Staff Member at IBM Research, enjoys creating systems to solve problems beyond the reach of current technology.

 

Paul’s current project integrates secure, compliant AI capabilities with enterprise Hybrid Cloud allowing clients to extract new business value from their data.

 

Paul’s previous work includes the design and construction of distributed, and high-performance computing systems at CMU, Transarc, and IBM Research. Projects include The Andrew Project at CMU, ASCI White, IBM Global Storage Architecture, Blue Gene Supercomputers, IBM Cloud, and IBM Cognitive Systems. Paul has managed data centers, and brings his first-hand knowledge of these environments, combined with experience of automation and robustness, to the design of AI for Hybrid Cloud infrastructure.

1:45 PM - 2:10 PM
PRESENTATION

Innovation excites us and unlocks business value but unless it inherently scales profitably, you could be stuck at a dead-end. This talk looks at NVDIMM-N as a cautionary tale of commercialization pitfalls that kill innovative technologies. How can you analyse a technology not just for the value it unleashes but also for its long-term commercial viability? How is CXL different? What types of CXL implementations should you consider and which should you be wary of?

 

CXL
Emerging Memories
Use Case
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Keith Winkeler

VP of Engineering, PowerEdge & Core Compute Platforms
Dell Technologies

Keith Winkeler is VP of Engineering, PowerEdge & Core Compute Platforms at Dell Technologies. Keith is an accomplished and collaborative executive with 30 years of demonstrated excellence in building and leading high performance global organizations responsible for architectural definition, development and delivery of industry leading HW/SW products. His proven strengths include talent management and development, organizational design, matrixed and global teams, ODM partner leadership and value chain management.

Keith Winkeler

VP of Engineering, PowerEdge & Core Compute Platforms
Dell Technologies

Keith Winkeler is VP of Engineering, PowerEdge & Core Compute Platforms at Dell Technologies. Keith is an accomplished and collaborative executive with 30 years of demonstrated excellence in building and leading high performance global organizations responsible for architectural definition, development and delivery of industry leading HW/SW products. His proven strengths include talent management and development, organizational design, matrixed and global teams, ODM partner leadership and value chain management.

2:10 PM - 2:35 PM
PRESENTATION
CXL
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Matthew Burns

Technical Marketing Manager
Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

Matthew Burns

Technical Marketing Manager
Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

2:35 PM - 3:00 PM
AFTERNOON NETWORKING
3:00 PM - 3:45 PM
PANEL
CXL
Emerging Memories
External Memory
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Camberley Bates

Managing Director & Analyst
Evaluator Group

www.evaluatorgroup.com

Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.

Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.

She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.

 

Camberley Bates

Managing Director & Analyst
Evaluator Group

www.evaluatorgroup.com

Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.

Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.

She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.

 

Panellists

Author:

Samir Rajadnya

Principal Architect
Microsoft

Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.

Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.

Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.

Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.

Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture

 

 

Samir Rajadnya

Principal Architect
Microsoft

Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.

Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.

Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.

Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.

Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture

 

 

Author:

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

Author:

Ahmad Danesh

Associate Vice President, Product Management
Astera Labs

Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.


Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.

Ahmad Danesh

Associate Vice President, Product Management
Astera Labs

Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.


Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.

Author:

Mahesh Wagh

Senior Fellow & Server System Architect
AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Mahesh Wagh

Senior Fellow & Server System Architect
AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Author:

Siamak Tavallaei

Advisor to the Board
CXL Consortium

Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management.  In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack).  His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

Siamak Tavallaei

Advisor to the Board
CXL Consortium

Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management.  In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack).  His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

3:45 PM - 4:30 PM
PANEL

•        Computational Storage and Memory

•        CXL and UCIe 

•        Emerging Persistent Memory Types 

•        Bridging to the Application Layer 

Use Case
Embedded Memory
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Tom Coughlin

President
Coughlin Associates

Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant.  He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.

Dr. Coughlin has many publications and six patents to his credit.  Tom is also the author of Digital Storage in Consumer Electronics:  The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services.  Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports.  Tom is also a regular contributor on digital storage for Forbes.com and other blogs.

Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations.  Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years.  He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV).  For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.

Tom Coughlin

President
Coughlin Associates

Tom Coughlin, President, Coughlin Associates is a widely respected digital storage analyst as well as business and technology consultant.  He has over 40 years in the data storage industry with engineering and management positions at several companies as well as 20 years as a respected consultant.

Dr. Coughlin has many publications and six patents to his credit.  Tom is also the author of Digital Storage in Consumer Electronics:  The Essential Guide, which is now in it’s second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage sndf Memory Technical and Business Consulting services.  Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports.  Tom is also a regular contributor on digital storage for Forbes.com and other blogs.

Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI), the IEEE (he is Past President of IEEE-USA, Past Chair of the IEEE New Initiatives Committee, Past Chair of the IEEE Public Visibility Committee, Past Director for IEEE Region 6, Past Chair and still active in the IEEE Santa Clara Valley section and active in the Consumer Technology Society) and other professional organizations.  Tom is the founder and organizer of the Storage Visions Conferences (www.storagevisions.com as well as the Creative Storage Conferences (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years.  He is an IEEE Fellow, HKN member, and a board member of the Consultants Network of Silicon Valley (CNSV).  For more information on Tom Coughlin and his publications go to www.tomcoughlin.com.

Author:

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

David McIntyre

Director, Product Planning: Samsung & Board Member: SNIA
SNIA

Author:

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Arvind Jagannath

Lead Platform Product Manager
VMWare

Arvind Jagannath works in Product Management at VMware. With over 25 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from the University of Chicago, Booth school of Business and a Bachelors in Computer Science and Engineering.

Author:

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Debendra Das Sharma

TTF Co-Chair: CXL Consortium & Senior Fellow: Intel
CXL Consortium

Debendra Das Sharma (Senior Member, IEEE) was born in Odisha, India, in 1967. He received the B.Tech. degree (Hons.) in computer science and engineering from IIT Kharagpur, Kharagpur, India, in 1989, and the Ph.D. degree in computer systems engineering from the University of Massachusetts, Amherst, MA, USA, in 1995.,He joined Hewlett-Packard, Roseville, CA, USA, in 1994, and Intel, Santa Clara, CA, USA, in 2001. He is currently an Senior Fellow with Intel. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), Coherency Interconnect, Multi-Chip Package Interconnect, and Rack Scale Architecture. He has been leading the development of PCI-Express, CXL, and UCIe inside Intel as well as across the industry since their inception. He holds 160+ U.S. patents and more than 400 patents worldwide.,Dr. Das Sharma has been awarded the Distinguished Alumnus Award by IIT, in 2019, the 2021 IEEE Region 6 Engineer of the Year Award, the PCI-SIG Lifetime Contribution Award in 2022, and the 2022 IEEE CAS Industrial Pioneer Award. He is currently the Chair of UCIe Board, a Director of PCI-SIG Board, and the Chair of the CXL Board

Author:

Arthur Sainio

Director, Product Marketing
Smart Modular Technologies

Arthur Sainio is Co-Chair of the SNIA Persistent Memory and NVDIMM Special Interest Group, which accelerates the awareness and adoption of Persistent Memories and NVDIMMs for computing architectures.

As a Director of Product Marketing at SMART Modular Technologies. Arthur has been driving new product launch and business development activities at SMART since 1998.

Prior to Smart, Arthur worked as a product manager at Hitachi Semiconductor America. While there, his focus was on DRAM, SRAM, and Flash technologies.

Arthur holds a MBA from San Francisco State University and a MS from Arizona State
University.

Arthur Sainio

Director, Product Marketing
Smart Modular Technologies

Arthur Sainio is Co-Chair of the SNIA Persistent Memory and NVDIMM Special Interest Group, which accelerates the awareness and adoption of Persistent Memories and NVDIMMs for computing architectures.

As a Director of Product Marketing at SMART Modular Technologies. Arthur has been driving new product launch and business development activities at SMART since 1998.

Prior to Smart, Arthur worked as a product manager at Hitachi Semiconductor America. While there, his focus was on DRAM, SRAM, and Flash technologies.

Arthur holds a MBA from San Francisco State University and a MS from Arizona State
University.

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