Innovation excites us and unlocks business value but unless it inherently scales profitably, you could be stuck at a dead-end. This talk looks at NVDIMM-N as a cautionary tale of commercialization pitfalls that kill innovative technologies. How can you analyse a technology not just for the value it unleashes but also for its long-term commercial viability? How is CXL different? What types of CXL implementations should you consider and which should you be wary of?

The leading companies at every level of the data center value chain, from IP, chips, platforms, system OEMs to hyperscalers, are coalescing around CXL technology as a path to revolutionize the data center. With workload demands increasing rapidly, the need for more memory bandwidth and capacity continues to rise. Memory is of critical importance, and its share of the server bill of materials (BoM) continues to grow. Making the best use of vital memory resources is an imperative. With CXL technology, the industry is pursuing tiered-memory solutions that can break through the memory bottleneck while at the same time delivering greater efficiency and improved TCO. Ultimately, CXL technology can support composable architectures that match the amount of compute, memory and storage in an on-demand fashion to the needs of a wide range of advanced workloads.    

Enterprise knowledge graphs (EKGs) offer the ability to store large connected datasets in memory for fast traversal using simple pointer-hopping instructions.  However, keeping hundreds or thousands of cores feed with traversal data has become one of the key challenges for artificial intelligence and analytics.  Despite the exponential growth in graphs databases we have yet to see hardware tuned to graph analytics workloads.  In this session we will review the requirements for EKGs and provide a roadmap of how new memory hardware can be used to solve EKG challenges.

The AI ´memory wall´is well documented, where AIML applications are hitting bottlenecks in intra/inter-chip and communication across/to AIML accelerators. Memory requirements to train AIML models are typically several times larger than the number of parameters, while the speed of data transfer has consistently failed to keep up with advancements in compute capabilities.

In the innovative world of dedicated AIML processors and systems, there have been a variety of approaches, both at the chip and systems level, to engineering around these challenges. This panel will look at how leading engineering teams working in this space are tackling the AI memory wall and how they see requirements shifting as requirements for new types of models evolve.

With current trends in DRAM capacities and costs, in-memory database technology is rapidly becoming mainstream. Oracle Database In-Memory features a unique dual-format in-memory architecture designed to optimize the performance of simultaneous analytic and transactional workloads on the same data. In addition, the in-memory columnar technology for Oracle Database In-Memory is also available within the storage tier of the Exadata database machine, allowing for effective in-memory columnar capacities to approach 100s of Terabytes.  In-memory processing is more than simply about speed; it enables a fundamental transformation in business processes. Just as air travel enabled more than faster travel - it fundamentally changed society, Oracle Database In-Memory similarly enables not just faster analytics and transactions, but a fundamental rethinking and drastic simplification of the traditional analytic architectures. In this session we will show how, especially when combined with Oracle's many converged database capabilities, Database In-Memory allows for the development of a new class of real-time enterprise applications, with significant reduction in cost and complexity, while providing unmatched performance across a wide range of workloads.

As the cost of sequencing drops and the quantity of data produced by sequencing grows, the amount of processing dedicated to genomics is increasing at a rapid pace.  Genomics is evolving in a number of directions simultaneously.  Some key applications scale naturally to use resources available in the cloud, while other computations benefit from on-prem acceleration using FPGAs or GPUs.  All of these computations strain the bandwidth and capacity of available resources.  In this talk, Roche´s Tom Sheffler will share an overview of the memory-bound challenges present in genomics and venture some possible solutions.

Recent work by the National Energy Technology Laboratory and Cerebras Systems Inc, has underscored the critical needs of sufficient bandwidth and latency in scientific computing.  In this work, the team demonstrated (to the best of our knowledge) the fastest solution to field equations in computing history.  These remarkable results were made possible by the trifecta of great memory bandwidth, great interconnect bandwidth, and amazing (one clock cycle) communication latency and injection rate for small messages.  Furthermore, the bandwidths are sufficiently high such that no memory hierarchy is necessary which significantly simplifies programming models and software development effort and expense.  In this talk we will outline the conditions necessary to achieve these results.

Working back from the question,"what do future systems architectures need to look like?", this panel will investigate the current memory, bandwidth and latency bottlenecks in systems today, and compare and contrast datacenter and HPC examples. In discussing the characteristics, similarities, and differences between various server workloads and use cases, such as AIML co-design, acceleration of scientific workloads and others, this panel will attempt to establish context for why memory innovation is so important.