TRACK A: Hardware & Systems: Design and Deployment of AI Engines | Kisaco Research

We have witnessed a big paradigm shift in how AI has affected our daily lives. While AI model training is typically done in a cloud infrastructure setting, model inferencing has seen a greater explosion on power, area, bandwidth and memory constrained edge devices. 

These inferencing workloads have varying high computational and memory needs, stringent power and silicon area requirements that can be very challenging to meet. This talk will try to bring out the design philosophies and challenges around designing AI hardware accelerators. We are witnessing a new era in how AI led innovation is affecting the next generation of embedded hardware and software design alike.

Session Topics: 
Chip Design
Novel AI Hardware
Speaker(s): 

Author:

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems