Systems Engineering | Kisaco Research

Systems Engineering

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Edge AI
Enterprise AI
ML at Scale
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Vinesh Sukumar

Senior Director & Head of AI/ML Product Management
Qualcomm

Vinesh Sukumar currently serves as Senior Director – Head of AI/ML product management at Qualcomm Technologies, Inc (QTI).  In this role, he leads AI product definition, strategy and solution deployment across multiple business units.

•He has about 20 years of industry experience spread across research, engineering and application deployment. He currently holds a doctorate degree specializing in imaging and vision systems while also completing a business degree focused on strategy and marketing. He is a regular speaker in many AI industry forums and has authored several journal papers and two technical books.

Vinesh Sukumar

Senior Director & Head of AI/ML Product Management
Qualcomm

Vinesh Sukumar currently serves as Senior Director – Head of AI/ML product management at Qualcomm Technologies, Inc (QTI).  In this role, he leads AI product definition, strategy and solution deployment across multiple business units.

•He has about 20 years of industry experience spread across research, engineering and application deployment. He currently holds a doctorate degree specializing in imaging and vision systems while also completing a business degree focused on strategy and marketing. He is a regular speaker in many AI industry forums and has authored several journal papers and two technical books.

Author:

Barrie Mullins

VP, Product
Flex Logix

Barrie has 25+ years of experience working with edge, embedded and AI systems across multiple industries including industrial, automotive, robotics, storage, and communications. Previously, he spent a year at Blaize as head of marketing, and three years at NVIDIA where he led the Jetson Product Marketing team. Prior to NVIDIA, he held multiple roles in Xilinx, including leading product marketing and management for the Zynq product line, sales enablement, business development, customer program management and managing design services. Barrie moved to the United States in 2007 from Ireland, where he worked for Xilinx and two starts ups, Raidtec Corp. and Eurologic Systems, in the Data Storage space where he holds three patents.  

Barrie received his EE from the Munster Technological University, an ME from University College Dublin and an MBA from Santa Clara University’s Leavey School of Business. 

Barrie Mullins

VP, Product
Flex Logix

Barrie has 25+ years of experience working with edge, embedded and AI systems across multiple industries including industrial, automotive, robotics, storage, and communications. Previously, he spent a year at Blaize as head of marketing, and three years at NVIDIA where he led the Jetson Product Marketing team. Prior to NVIDIA, he held multiple roles in Xilinx, including leading product marketing and management for the Zynq product line, sales enablement, business development, customer program management and managing design services. Barrie moved to the United States in 2007 from Ireland, where he worked for Xilinx and two starts ups, Raidtec Corp. and Eurologic Systems, in the Data Storage space where he holds three patents.  

Barrie received his EE from the Munster Technological University, an ME from University College Dublin and an MBA from Santa Clara University’s Leavey School of Business. 

Author:

Vinay Palakkode

Senior Staff ML Engineer & Manager
Rivian

“Vinay Palakkode is a senior staff machine learning engineer and manages a team of deep learning researchers and engineers at Rivian Automotive’s self-driving organization. Vinay holds a master’s degree in electrical and computer engineering from Carnegie Mellon University. He specializes in perception for robotics and high-performance computing. Vinay held prior engineering and management positions at Apple’s Technology Development Group (TDG) and Special Projects Groups (SPG).”

Vinay Palakkode

Senior Staff ML Engineer & Manager
Rivian

“Vinay Palakkode is a senior staff machine learning engineer and manages a team of deep learning researchers and engineers at Rivian Automotive’s self-driving organization. Vinay holds a master’s degree in electrical and computer engineering from Carnegie Mellon University. He specializes in perception for robotics and high-performance computing. Vinay held prior engineering and management positions at Apple’s Technology Development Group (TDG) and Special Projects Groups (SPG).”

Author:

Vamsi Nalluri

Machine Learning HW Architect
Rivian

Vamsi is ML HW Architect at Rivian, and has 17 years of experience in the semiconductor industry working on architecture, verification, and validation.


He most recently was at Xilinx, where he has accelerated sparse neural networks to achieve 3X hardware performance improvement on the 7nm flagship technology platform from Xilinx on many of the industry standard networks like ResNetv50, Yolo and other CNN benchmarks.

Prior to that, he has architected and trained dataflow implementations of quantized and mixed precision neural networks at Intel. 

He graduated from IIT Madras with a B.Tech in Electrical Engineering and is a big tennis fan - which includes playing and watching

Vamsi Nalluri

Machine Learning HW Architect
Rivian

Vamsi is ML HW Architect at Rivian, and has 17 years of experience in the semiconductor industry working on architecture, verification, and validation.


He most recently was at Xilinx, where he has accelerated sparse neural networks to achieve 3X hardware performance improvement on the 7nm flagship technology platform from Xilinx on many of the industry standard networks like ResNetv50, Yolo and other CNN benchmarks.

Prior to that, he has architected and trained dataflow implementations of quantized and mixed precision neural networks at Intel. 

He graduated from IIT Madras with a B.Tech in Electrical Engineering and is a big tennis fan - which includes playing and watching

Author:

Hui Wang

Machine Learning Engineer
Schlumberger

Hui Wang

Machine Learning Engineer
Schlumberger

RISC-V adoption has increased dramatically throughout 2022, due to the architecture's simple intruction set, the ability to better pre-process NNs for acceleration and its open source nature. The advent of the RISC-V vector extension allows AI processor builders to develop on top of instructions that other companies are using and then innovate in whatever domain they want to specialize in.


Chip Design
Edge AI
ML at Scale
Novel
Systems Design
Hardware Engineering
Strategy
Systems Engineering

Author:

Bing Yu

Senior Technical Director
Andes Technology

Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

Bing Yu

Senior Technical Director
Andes Technology

Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

Cerebras Systems builds the fastest AI accelerators in the industry. In this talk we will review how the size and scope of massive natural language processing (NLP) presents fundamental challenges to legacy compute and to traditional cloud providers. We will explore the importance of guaranteed node to node latency in large clusters, how that can’t be achieved in the cloud, and how it prevents linear and even deterministic scaling. We will examine the complexity of distributing NLP models over hundreds or thousands of GPUs and show how quickly and easily a cluster of Cerebras CS-2s is set up, and how linear scaling can be achieved over millions of compute cores with Cerebras technology. And finally, we will show how innovative customers are using clusters of Cerebras CS-2s to train large language models in order to solve both basic and applied scientific challenges, including understanding the COVID-19 replication mechanism, epigenetic language modelling for drug discovery, and in the development of clean energy. This enables researchers to test ideas that may otherwise languish for lack of resources and, ultimately, reduces the cost of curiosity.  ​

 

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

Graphcore's Intelligence Processing Unit (IPU), built on its unique wafer-on-wafer technology architecture, enables innovators across all industries to undertake breakthrough research with the power of AI compute. To deliver what Graphcore believes will be the standard for machine intelligence compute, it follows a continuous integration (CI) and continuous delivery (CD) process to ensure incremental code changes are delivered quickly and reliably to production. In this workshop, Graphcore will share how it’s using Synopsys formal verification solutions throughout the CI/CD process to deliver bug-free silicon.  Workshop topics include:

  • An introduction to Sequential Equivalence Checking (SEQ) and Formal Testbench Analyzer (FTA) applications, part of Synopsys VC Formal
  • Graphcore’s formal verification deployment to maximize engineering productivity
  • How formal is modified for CI and CD
  • Strategies Graphcore employed to overcome reproducibility challenges at the CI stage

 

Hardware Engineer workshop are restricted to hardware engineers and architects, and software designers from companies interested in learning how to design and deploy ML onto hardware platforms.

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a hardware or software engineer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Chip Design
Novel AI Hardware
Systems Design
Hardware Engineering
Systems Engineering

Author:

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

Author:

Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.

Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.

This presentation, by the RISC-V founder, will highlight how RISC-V and vector compute are gaining momentum with AI and ML and computer vision and how it addresses challenges like managing power consumption, extra data movement, the need for multiple libraries, and issues with generational incompatibility. To solve these obstacles, many of the world’s largest data and device companies are turning to vector processing based on the RISC‑V Vector (RVV) 1.0 ISA.

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Hardware Engineering
Systems Engineering
Strategy

Author:

Krste Asanovic

Co-Founder & Chief Architect
SiFive

Krste is SiFive’s Chief Architect and a Co-Founder. He is also a Professor in the EECS Department at the University of California, Berkeley, where he also serves as Director of the ADEPT Lab. Krste leads the RISC‑V ISA project at Berkeley and is Chairman of the RISC‑V Foundation. He is an ACM Fellow and an IEEE Fellow. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge.

Krste Asanovic

Co-Founder & Chief Architect
SiFive

Krste is SiFive’s Chief Architect and a Co-Founder. He is also a Professor in the EECS Department at the University of California, Berkeley, where he also serves as Director of the ADEPT Lab. Krste leads the RISC‑V ISA project at Berkeley and is Chairman of the RISC‑V Foundation. He is an ACM Fellow and an IEEE Fellow. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge.

Deep neural networks (DNNs), a subset of machine learning (ML), provide a foundation for automating conversational artificial intelligence (CAI) applications. FPGAs provide hardware acceleration enabling high-density and low latency CAI. In this presentation, we will provide an overview of CAI, data center use-cases, describe the traditional compute model and its limitations and show how an ML compute engine integrated into the Achronix FPGA can lead to 90% cost reductions for speech transcription.

 

Enterprise AI
NLP
Novel AI Hardware
ML at Scale
Data Science
Hardware Engineering
Software Engineering
Systems Engineering

Author:

Salvador Alvarez

Senior Manager, Product Planning
Achronix
  • Salvador Alvarez is the Senior Manager of Product Planning at Achronix, coordinating the research, development, and launch of new Achronix products and solutions. With over 20 years of experience in product growth, roadmap development, and competitive intelligence and analysis in the semiconductor, automotive, and edge AI industries, Sal Alvarez is a recognized expert in helping customers realize the advantages of edge AI and deep learning technology over legacy cloud AI approaches. Sal holds a B.S. in computer science and electrical engineering from the Massachusetts Institute of Technology.​

Salvador Alvarez

Senior Manager, Product Planning
Achronix
  • Salvador Alvarez is the Senior Manager of Product Planning at Achronix, coordinating the research, development, and launch of new Achronix products and solutions. With over 20 years of experience in product growth, roadmap development, and competitive intelligence and analysis in the semiconductor, automotive, and edge AI industries, Sal Alvarez is a recognized expert in helping customers realize the advantages of edge AI and deep learning technology over legacy cloud AI approaches. Sal holds a B.S. in computer science and electrical engineering from the Massachusetts Institute of Technology.​

As AI makes its way into healthcare and medical applications, the role of hardware accelerators in the successful deployment of such large AI models becomes more and more important. Nowadays large language models, such as GPT-3 and T5, offer unprecedented opportunities to solve challenging healthcare business problems like drug discovery, medical term mapping and insight generation from electronic health records. However, efficient and cost effective training, as well as deployment and maintenance of such models in production remains a challenge for healthcare industry. This presentation will review a few open challenges and opportunities in the healthcare industry and the benefits that AI hardware innovation may bring to the ML utilization.

Developer Efficiency
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Hooman Sedghamiz

Director of AI & ML
Bayer

Hooman Sedghamiz is Director of AI & ML at Bayer. He has lead algorithm development and generated valuable insights to improve medical products ranging from implantable, wearable medical and imaging devices to bioinformatics and pharmaceutical products for a variety of multinational medical companies.

He has lead projects, data science teams and developed algorithms for closed loop active medical implants (e.g. Pacemakers, cochlear and retinal implants) as well as advanced computational biology to study the time evolution of cellular networks associated with cancer , depression and other illnesses.

His experience in healthcare also extends to image processing for Computer Tomography (CT), iX-Ray (Interventional X-Ray) as well as signal processing of physiological signals such as ECG, EMG, EEG and ACC.

Recently, his team has been working on cutting edge natural language processing and developed cutting edge models to address the healthcare challenges dealing with textual data.

Hooman Sedghamiz

Director of AI & ML
Bayer

Hooman Sedghamiz is Director of AI & ML at Bayer. He has lead algorithm development and generated valuable insights to improve medical products ranging from implantable, wearable medical and imaging devices to bioinformatics and pharmaceutical products for a variety of multinational medical companies.

He has lead projects, data science teams and developed algorithms for closed loop active medical implants (e.g. Pacemakers, cochlear and retinal implants) as well as advanced computational biology to study the time evolution of cellular networks associated with cancer , depression and other illnesses.

His experience in healthcare also extends to image processing for Computer Tomography (CT), iX-Ray (Interventional X-Ray) as well as signal processing of physiological signals such as ECG, EMG, EEG and ACC.

Recently, his team has been working on cutting edge natural language processing and developed cutting edge models to address the healthcare challenges dealing with textual data.

One of the biggest challenges in the US is managing the cost of healthcare.  Although we have high healthcare costs in the US, our life expectancy is still average.  In this talk we will look at some of the core causes of healthcare costs and what modern AI hardware can do to lower these costs.  We will see that faster and bigger GPUs alone will not save us.  We need detailed models to across a wide swath of our communities and perform early interventions.  We need accurate models of our world and the ability to simulate the impact of policy changes to overall healthcare costs.  We need new MIMD hardware with cores and memory architecture that keep cores fed with the right data.

Enterprise AI
ML at Scale
Systems Design
Data Science
Software Engineering
Systems Engineering

Author:

Dan McCreary

Distinguished Engineer, Graph & AI
Optum

Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.

Dan McCreary

Distinguished Engineer, Graph & AI
Optum

Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.

Chip Design
Edge AI
Enterprise AI
Novel AI Hardware
Systems Design
Hardware Engineering
Software Engineering
Systems Engineering

Author:

Harshit Khaitan

Director, AI Accelerators
Meta

Harshit Khaitan is the Director of AI Accelerator at Meta where he leads building AI Accelerators for Reality labs products. Prior to Meta, he was technical lead and co-founder for the Edge Machine learning accelerators at Google, responsible for MLA in Google Pixel 4 (Neural Core) and Pixel 6 (Google Tensor SoC). He has also held individual and technical leadership positions at Google’s first Cloud TPU, Nvidia Tegra SoCs and Nvidia GPUs. He has 10+ US and international patents in On-device AI acceleration. He has a Master’s degree in Computer Engineering from North Carolina State University and a Bachelor’s degree in Electrical Engineering from Manipal Institute of Technology, India.

Harshit Khaitan

Director, AI Accelerators
Meta

Harshit Khaitan is the Director of AI Accelerator at Meta where he leads building AI Accelerators for Reality labs products. Prior to Meta, he was technical lead and co-founder for the Edge Machine learning accelerators at Google, responsible for MLA in Google Pixel 4 (Neural Core) and Pixel 6 (Google Tensor SoC). He has also held individual and technical leadership positions at Google’s first Cloud TPU, Nvidia Tegra SoCs and Nvidia GPUs. He has 10+ US and international patents in On-device AI acceleration. He has a Master’s degree in Computer Engineering from North Carolina State University and a Bachelor’s degree in Electrical Engineering from Manipal Institute of Technology, India.