AI Hardware Summit Agenda

AI Hardware Summit Agenda

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Tuesday, 13 Sep, 2022
9:00 - 9:45 AM

Developer workshops are restricted to machine learning practitioners from research institutions and enterprises who are interested in learning how to port code onto novel AI platforms and want to get hands-on access to hardware and SDKs.  


Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a machine learning engineer / AI application developer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Developer Efficiency
Edge AI
Enterprise AI
ML at Scale
Data Science
Software Engineering

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

... read more

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Régis Pierrard

Machine Learning Engineer
HuggingFace
... read more

Régis Pierrard

Machine Learning Engineer
HuggingFace

Author:

Philipp Schmid

Tech Lead
HuggingFace
... read more

Philipp Schmid

Tech Lead
HuggingFace
9:45 AM - 10:45 AM

Using Hugging Face Optimum, we will show how easy it is to run and accelerate an end-to-end state-of-the-art Transformer model workflow on IPUs. We’ll provide a demo to fine-tune a BERT-Large Transformer model in IPUs using Hugging Face Optimum, and then serve the model using the inference API. Join us as we look under the hood of our Intelligence Processing Unit to see how our unique architecture, combined with Optimum’s simple plug-and-play experience, enables faster performance on today’s most popular ML models. By the end of the talk, we would like you to have a better understanding of the wide range of off-the-shelf NLP & Computer Vision Transformer models through our integration with the Hugging Face ecosystem. Plus, how to access this walkthrough by using our free IPU runtimes in the cloud.

Developer workshops are restricted to machine learning practitioners from research institutions and enterprises who are interested in learning how to port code onto novel AI platforms and want to get hands-on access to hardware and SDKs.  


Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a machine learning engineer / AI application developer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.


Developer Efficiency
Novel AI Hardware
Data Science
Software Engineering
Host

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

... read more

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Régis Pierrard

Machine Learning Engineer
HuggingFace
... read more

Régis Pierrard

Machine Learning Engineer
HuggingFace

Author:

Philipp Schmid

Tech Lead
HuggingFace
... read more

Philipp Schmid

Tech Lead
HuggingFace

Author:

Tim Santos

Developer Relations Director
Graphcore

Tim is leading the Developer Relations in Graphcore to help the AI & ML community achieve maximum success with IPUs and make the next breakthroughs in machine intelligence. Tim has worn many developer hats in his career, from being a research engineer, data scientist and leading MLOps teams. Along the way, he’s gained experience across all stages of the development lifecycle taking AI applications from experimentation to deployment. If you’re looking to try out IPUs, learn more about our Poplar SDK and tools, showcase your innovations, connect with the community, request educational resources, or provide feedback on our technology, then Tim is your champion.

... read more

Tim Santos

Developer Relations Director
Graphcore

Tim is leading the Developer Relations in Graphcore to help the AI & ML community achieve maximum success with IPUs and make the next breakthroughs in machine intelligence. Tim has worn many developer hats in his career, from being a research engineer, data scientist and leading MLOps teams. Along the way, he’s gained experience across all stages of the development lifecycle taking AI applications from experimentation to deployment. If you’re looking to try out IPUs, learn more about our Poplar SDK and tools, showcase your innovations, connect with the community, request educational resources, or provide feedback on our technology, then Tim is your champion.

10:45 AM - 11:30 AM
Networking Break
11:30 AM - 12:30 PM

Developer workshops are restricted to machine learning practitioners from research institutions and enterprises who are interested in learning how to port code onto novel AI platforms and want to get hands-on access to hardware and SDKs. 

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a machine learning engineer / AI application developer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Developer Efficiency
Novel AI Hardware
Data Science
Software Engineering
Host

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

... read more

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Régis Pierrard

Machine Learning Engineer
HuggingFace
... read more

Régis Pierrard

Machine Learning Engineer
HuggingFace

Author:

Philipp Schmid

Tech Lead
HuggingFace
... read more

Philipp Schmid

Tech Lead
HuggingFace
12:30 PM - 1:45 PM
Lunch
1:45 PM - 2:45 PM

During this workshop, attendees will be updated on the state of the art in computer vision use cases and learn how to build deep learning models for object detection, while improving model performance. Atos' expert host will provide best practices on team organization to facilitate success. Finally, attendees will learn how to implement an engineering strategy - build a project template & data versioning, experiment tracking & feedback, leverage testing & boost model promotion.

Developer workshops are restricted to machine learning practitioners from research institutions and enterprises who are interested in learning how to port code onto novel AI platforms and want to get hands-on access to hardware and SDKs. 

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a machine learning engineer / AI application developer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Developer Efficiency
Edge AI
Novel AI Hardware
Data Science
Software Engineering

Author:

Ashwin Sakhare

Senior Data Scientist, Atos zData
Atos

Ashwin Sakhare, PhD is a Senior Data Scientist at Atos zData, a leading AI and Data Science firm. Ashwin leverages over a decade of industry and research experience to solve key business challenges through novel product development and data-driven machine learning approaches. He is a computer vision expert and has delivered AI and machine vision solutions to clients across a broad range of application domains. He has a strong healthcare industry background, where he led the ideation, design, and development of AI products. Ashwin holds a BS in Biomedical Engineering from North Carolina State University and a MS and PhD in Biomedical Engineering from the University of Southern California.

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Ashwin Sakhare

Senior Data Scientist, Atos zData
Atos

Ashwin Sakhare, PhD is a Senior Data Scientist at Atos zData, a leading AI and Data Science firm. Ashwin leverages over a decade of industry and research experience to solve key business challenges through novel product development and data-driven machine learning approaches. He is a computer vision expert and has delivered AI and machine vision solutions to clients across a broad range of application domains. He has a strong healthcare industry background, where he led the ideation, design, and development of AI products. Ashwin holds a BS in Biomedical Engineering from North Carolina State University and a MS and PhD in Biomedical Engineering from the University of Southern California.

Deploying a neural network on an embedded solution requires more than compiling a trained model. Join us to discuss the IP and tooling available from Cadence that allow architects to start with a neural network model, run through quantization and partitioning mapping to a configurable embedded target, simulating the design to get performance data (both cycle and energy), and iterating through design optimizations to reach an optimal implementation. Our experts will give a technical walkthrough of the tools, features, supported frameworks, and infrastructure available to both software and silicon designers.

Hardware Engineer workshop are restricted to hardware engineers and architects, and software designers from companies interested in learning how to design and deploy ML onto hardware platforms.

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a hardware or software engineer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

 

Chip Design
Edge AI
Novel AI Hardware
Hardware Engineering

Author:

Ade Bamidele

Design Engineering Architect
Cadence Design Systems

Ade is an Architect in the Tensilica Central Applications Team. Ade focuses on the optimization and acceleration of imaging and vision algorithms on Vision and AI DSP and engines. He has over 15 years of experience in the R&D and optimization of computer vision and pattern recognition algorithms on vision and embedded devices. Ade graduated from University College London in 2006 with a Doctoral in Electronics Engineering and Thesis focusing on Computational Visual Attention.

... read more

Ade Bamidele

Design Engineering Architect
Cadence Design Systems

Ade is an Architect in the Tensilica Central Applications Team. Ade focuses on the optimization and acceleration of imaging and vision algorithms on Vision and AI DSP and engines. He has over 15 years of experience in the R&D and optimization of computer vision and pattern recognition algorithms on vision and embedded devices. Ade graduated from University College London in 2006 with a Doctoral in Electronics Engineering and Thesis focusing on Computational Visual Attention.

Author:

Michael Hubrig

Sr Design Engineering Architect
Cadence Design Systems

Michael is Sr. Architect in the Tensilica Central Applications Team. His team provides deep technical support for Vision and AI DSP and engines. Michael has 20 years of experience porting imaging and vision algorithms to DSP platforms.

... read more

Michael Hubrig

Sr Design Engineering Architect
Cadence Design Systems

Michael is Sr. Architect in the Tensilica Central Applications Team. His team provides deep technical support for Vision and AI DSP and engines. Michael has 20 years of experience porting imaging and vision algorithms to DSP platforms.

Author:

Rohan Darole

Sr Principal Design Engineer
Cadence Design Systems

Rohan Darole is a ML Product Specialist at Cadence TIP (Tensilica IP Group). He received his Master’s in Computer Science from SUNY-UB, Buffalo, NY. Rohan is leading a team of application engineers responsible for definition, realization, and customer engagements of Tensilica AI MAX Product Family. Previously he has worked on CV/ML Acceleration with Vision DSPs, Imaging (ISP) & Video Codecs SW Development.

... read more

Rohan Darole

Sr Principal Design Engineer
Cadence Design Systems

Rohan Darole is a ML Product Specialist at Cadence TIP (Tensilica IP Group). He received his Master’s in Computer Science from SUNY-UB, Buffalo, NY. Rohan is leading a team of application engineers responsible for definition, realization, and customer engagements of Tensilica AI MAX Product Family. Previously he has worked on CV/ML Acceleration with Vision DSPs, Imaging (ISP) & Video Codecs SW Development.

2:45 PM - 3:00 PM
Break
3:00 PM - 4:00 PM

State-of-the-art large language models (LLMs) are empowering organizations to unlock the most critical insights in their unstructured data. Despite the opportunities, the cost and complexity of developing these models internally makes them impractical for most organizations to develop on their own. SambaNova overcomes these challenges with production-ready, pre-trained LLMs delivered through a full-stack solution, which can be further adapted through unlimited fine-tuning or pre-training within an organization’s own environment. In this workshop, we will showcase prototyping solutions for enterprise semantic search, legal compliance analysis, and call center service analysis, built on top of pretrained LLMs available through SambaNova Dataflow-as-a-Service. This is followed by live trials on the demo to showcase the exciting potential of large language models.

Developer workshops are restricted to machine learning practitioners from research institutions and enterprises who are interested in learning how to port code onto novel AI platforms and want to get hands-on access to hardware and SDKs. 

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a machine learning engineer / AI application developer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Developer Efficiency
NLP
Novel AI Hardware
Data Science
Software Engineering

Author:

Jian Zhang

Director, Machine Learning
SambaNova Systems
... read more

Jian Zhang

Director, Machine Learning
SambaNova Systems

Graphcore's Intelligence Processing Unit (IPU), built on its unique wafer-on-wafer technology architecture, enables innovators across all industries to undertake breakthrough research with the power of AI compute. To deliver what Graphcore believes will be the standard for machine intelligence compute, it follows a continuous integration (CI) and continuous delivery (CD) process to ensure incremental code changes are delivered quickly and reliably to production. In this workshop, Graphcore will share how it’s using Synopsys formal verification solutions throughout the CI/CD process to deliver bug-free silicon.  Workshop topics include:

  • An introduction to Sequential Equivalence Checking (SEQ) and Formal Testbench Analyzer (FTA) applications, part of Synopsys VC Formal
  • Graphcore’s formal verification deployment to maximize engineering productivity
  • How formal is modified for CI and CD
  • Strategies Graphcore employed to overcome reproducibility challenges at the CI stage

 

Hardware Engineer workshop are restricted to hardware engineers and architects, and software designers from companies interested in learning how to design and deploy ML onto hardware platforms.

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a hardware or software engineer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Chip Design
Novel AI Hardware
Systems Design
Hardware Engineering
Systems Engineering

Author:

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

... read more

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

Author:

Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.

... read more

Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.

4:00 PM - 7:00 PM

AI Hardware Summit attendees are invited to attend the an extended networking session where they can meet attendees from across both events. The Meet & Greet is a perfect opportunity to reconnect with peers, expand your network, and discuss the state of ML across the cloud-edge continuum!

Chip Design
Developer Efficiency
Edge AI
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Colin Murdoch

Chief Business Officer
DeepMind

Decades of international commercial experience and deep technical expertise mean Colin is uniquely placed to ensure DeepMind’s cutting-edge research benefits as many people as possible. As Chief Business Officer of DeepMind, he oversees a wide-range of teams including Applied, which applies research breakthroughs to Google products and infrastructure used by billions of people. He also helps drive the growth of DeepMind, building and leading critical functions including finance and strategy and leading external and commercial partnerships. Originally an electronics and software engineer, he has held senior positions at both start-ups and global companies such as Thomson Reuters, helping them solve their own complex, mission-critical, real-world challenges.

... read more

Colin Murdoch

Chief Business Officer
DeepMind

Decades of international commercial experience and deep technical expertise mean Colin is uniquely placed to ensure DeepMind’s cutting-edge research benefits as many people as possible. As Chief Business Officer of DeepMind, he oversees a wide-range of teams including Applied, which applies research breakthroughs to Google products and infrastructure used by billions of people. He also helps drive the growth of DeepMind, building and leading critical functions including finance and strategy and leading external and commercial partnerships. Originally an electronics and software engineer, he has held senior positions at both start-ups and global companies such as Thomson Reuters, helping them solve their own complex, mission-critical, real-world challenges.

Author:

Cade Metz

Technology Correspondent
New York Times

Cade Metz is a reporter with The New York Times, covering artificial intelligence, driverless cars, robotics, virtual reality, and other emerging areas. Genius Makers is his first book. Previously, he was a senior staff writer with Wired magazine and the U.S. editor of The Register, one of Britain’s leading science and technology news sites.

A native of North Carolina and a graduate of Duke University, Metz, 48, works in The New York Times’ San Francisco bureau and lives across the bay with his wife Taylor and two daughters.

... read more

Cade Metz

Technology Correspondent
New York Times

Cade Metz is a reporter with The New York Times, covering artificial intelligence, driverless cars, robotics, virtual reality, and other emerging areas. Genius Makers is his first book. Previously, he was a senior staff writer with Wired magazine and the U.S. editor of The Register, one of Britain’s leading science and technology news sites.

A native of North Carolina and a graduate of Duke University, Metz, 48, works in The New York Times’ San Francisco bureau and lives across the bay with his wife Taylor and two daughters.

Wednesday, 14 Sep, 2022
MAIN CONFERENCE: BUILDING AND OPTIMIZING ML PLATFORMS AT SCALE

Author:

Marshall Choy

SVP, Product
SambaNova Systems

Marshall Choy is Senior Vice President of Product at SambaNova Systems and is responsible for product management and go-to-market operations.  Marshall has extensive experience leading global organizations to bring breakthrough products to market, establish new market presences, and grow new and existing lines of business.  Marshall was previously Vice President of Product Management at Oracle until 2018.  He was responsible for the portfolio and strategy for Oracle Systems products and solutions.  He led teams that delivered comprehensive end-to-end hardware and software solutions and product management operations.  Prior to joining Oracle in 2010 when it acquired Sun Microsystems, he served as Director of Engineered Solutions at Sun.  During his 11 years there, Marshall held various positions in development, information technology, and marketing. 

... read more

Marshall Choy

SVP, Product
SambaNova Systems

Marshall Choy is Senior Vice President of Product at SambaNova Systems and is responsible for product management and go-to-market operations.  Marshall has extensive experience leading global organizations to bring breakthrough products to market, establish new market presences, and grow new and existing lines of business.  Marshall was previously Vice President of Product Management at Oracle until 2018.  He was responsible for the portfolio and strategy for Oracle Systems products and solutions.  He led teams that delivered comprehensive end-to-end hardware and software solutions and product management operations.  Prior to joining Oracle in 2010 when it acquired Sun Microsystems, he served as Director of Engineered Solutions at Sun.  During his 11 years there, Marshall held various positions in development, information technology, and marketing. 

8:30 AM - 9:00 AM
Luminary Keynote
Developer Efficiency
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Alexis Black Bjorlin

VP, Infrastructure Hardware
Meta

Dr. Alexis Black Bjorlin is VP, Infrastructure Hardware Engineering at Meta. She also serves on the board of directors at Digital Realty and Celestial AI. Prior to Meta, Dr. Bjorlin was Senior Vice President and General Manager of Broadcom’s Optical Systems Division and previously Corporate Vice President of the Data Center Group and General Manager of the Connectivity Group at Intel. Prior to Intel, she spent eight years as President of Source Photonics, where she also served on the board of directors. She earned a B.S. in Materials Science and Engineering from Massachusetts Institute of Technology and a Ph.D. in Materials Science from the University of California at Santa Barbara.

... read more

Alexis Black Bjorlin

VP, Infrastructure Hardware
Meta

Dr. Alexis Black Bjorlin is VP, Infrastructure Hardware Engineering at Meta. She also serves on the board of directors at Digital Realty and Celestial AI. Prior to Meta, Dr. Bjorlin was Senior Vice President and General Manager of Broadcom’s Optical Systems Division and previously Corporate Vice President of the Data Center Group and General Manager of the Connectivity Group at Intel. Prior to Intel, she spent eight years as President of Source Photonics, where she also served on the board of directors. She earned a B.S. in Materials Science and Engineering from Massachusetts Institute of Technology and a Ph.D. in Materials Science from the University of California at Santa Barbara.

9:00 AM - 9:30 AM
Chip Design
Edge AI
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering
Industry & Investment

Author:

Lip-Bu Tan

Executive Chairman
Cadence

Mr. Lip-Bu Tan is a Co-Founder, Partner, Managing Director, and Chairman of Walden International. Mr. Tan serves as Executive Chairman of Cadence Design Systems Inc., and as Chairman on the Board of SambaNova Systems, Inc. Mr. Tan also serves on the Boards of Softbank and Schneider Electric. Until late 2021, Mr Tan served as Chief Executive Officer at Cadence Design Systems Inc. since January 2009, serving as its President from January 2009 to November 2017. Lip-Bu focuses on semiconductor/components, cloud/big data, artificial intelligence and machine learning. Lip-Bu holds a B.S. in Physics from Nanyang University in Singapore, a M.S. in Nuclear Engineering from Massachusetts Institute of Technology, and a M.B.A. from the University of San Francisco. 

... read more

Lip-Bu Tan

Executive Chairman
Cadence

Mr. Lip-Bu Tan is a Co-Founder, Partner, Managing Director, and Chairman of Walden International. Mr. Tan serves as Executive Chairman of Cadence Design Systems Inc., and as Chairman on the Board of SambaNova Systems, Inc. Mr. Tan also serves on the Boards of Softbank and Schneider Electric. Until late 2021, Mr Tan served as Chief Executive Officer at Cadence Design Systems Inc. since January 2009, serving as its President from January 2009 to November 2017. Lip-Bu focuses on semiconductor/components, cloud/big data, artificial intelligence and machine learning. Lip-Bu holds a B.S. in Physics from Nanyang University in Singapore, a M.S. in Nuclear Engineering from Massachusetts Institute of Technology, and a M.B.A. from the University of San Francisco. 

9:30 AM - 9:55 AM

Cerebras Systems builds the fastest AI accelerators in the industry. In this talk we will review how the size and scope of massive natural language processing (NLP) presents fundamental challenges to legacy compute and to traditional cloud providers. We will explore the importance of guaranteed node to node latency in large clusters, how that can’t be achieved in the cloud, and how it prevents linear and even deterministic scaling. We will examine the complexity of distributing NLP models over hundreds or thousands of GPUs and show how quickly and easily a cluster of Cerebras CS-2s is set up, and how linear scaling can be achieved over millions of compute cores with Cerebras technology. And finally, we will show how innovative customers are using clusters of Cerebras CS-2s to train large language models in order to solve both basic and applied scientific challenges, including understanding the COVID-19 replication mechanism, epigenetic language modelling for drug discovery, and in the development of clean energy. This enables researchers to test ideas that may otherwise languish for lack of resources and, ultimately, reduces the cost of curiosity.  ​

 

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

... read more

Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

9:55 AM - 10:25 AM
Developer Efficiency
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Kunle Olukotun

Co-Founder & Chief Technologist
SambaNova Systems

Kunle Olukotun is the Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is a renowned pioneer in multi-core processor design and the leader of the Stanford Hydra chip multiprocessor (CMP) research project.

Prior to SambaNova Systems, Olukotun founded Afara Websystems to develop high-throughput, low-power multi-core processors for server systems. The Afara multi-core processor, called Niagara, was acquired by Sun Microsystems and now powers Oracle’s SPARC-based servers.

Olukotun is the Director of the Pervasive Parallel Lab and a member of the Data Analytics for What’s Next (DAWN) Lab, developing infrastructure for usable machine learning.

Olukotun is an ACM Fellow and IEEE Fellow for contributions to multiprocessors on a chip and multi-threaded processor design. Olukotun recently won the prestigious IEEE Computer Society’s Harry H. Goode Memorial Award and was also elected to the National Academy of Engineering—one of the highest professional distinctions accorded to an engineer.

Kunle received his Ph.D. in Computer Engineering from The University of Michigan.

... read more

Kunle Olukotun

Co-Founder & Chief Technologist
SambaNova Systems

Kunle Olukotun is the Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is a renowned pioneer in multi-core processor design and the leader of the Stanford Hydra chip multiprocessor (CMP) research project.

Prior to SambaNova Systems, Olukotun founded Afara Websystems to develop high-throughput, low-power multi-core processors for server systems. The Afara multi-core processor, called Niagara, was acquired by Sun Microsystems and now powers Oracle’s SPARC-based servers.

Olukotun is the Director of the Pervasive Parallel Lab and a member of the Data Analytics for What’s Next (DAWN) Lab, developing infrastructure for usable machine learning.

Olukotun is an ACM Fellow and IEEE Fellow for contributions to multiprocessors on a chip and multi-threaded processor design. Olukotun recently won the prestigious IEEE Computer Society’s Harry H. Goode Memorial Award and was also elected to the National Academy of Engineering—one of the highest professional distinctions accorded to an engineer.

Kunle received his Ph.D. in Computer Engineering from The University of Michigan.

Author:

Rodrigo Liang

Co-Founder & CEO
SambaNova Systems

Rodrigo is CEO and co-founder of SambaNova Systems. Prior to joining SambaNova, Rodrigo was responsible for SPARC Processor and ASIC Development at Oracle. He led the engineering organization responsible for the design of state-of-the-art processors and ASIC's for Oracle's enterprise servers.

... read more

Rodrigo Liang

Co-Founder & CEO
SambaNova Systems

Rodrigo is CEO and co-founder of SambaNova Systems. Prior to joining SambaNova, Rodrigo was responsible for SPARC Processor and ASIC Development at Oracle. He led the engineering organization responsible for the design of state-of-the-art processors and ASIC's for Oracle's enterprise servers.

10:25 AM - 10:50 AM

The true potential of AI rests on super-human learning capacity, and on the ability to selectively draw on that learning. Both of these properties – scale and selectivity – challenge the design of AI computers and the tools used to program them. A rich pool of new ideas is emerging, driven by a new breed of computing company, according to Graphcore co-founder Simon Knowles. At the AI Hardware Summit, Phil Brown, VP Scaled Systems Product discusses the creation of the Intelligence Processing Unit (IPU) – a new type of processor, specifically designed for AI computation. He looks ahead, towards the development of AIs with super-human cognition, and explores the nature of computation systems needed to make powerful AI an economic everyday reality.

Developer Efficiency
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Phil Brown

VP, Scaled Systems Product
Graphcore

Phil leads Graphcore’s efforts to build large scale AI/ML processing capability using Graphcore unique Intelligence Processing Units (IPUs) and IPU-Fabric and Streaming Memory technology. Previously he has held a number of different roles at Graphcore including Director of Applications, leading development of Graphcore’s flagship AL/ML models, and Director of Field Engineering, which acts as the focal point for technical engagements with our customers. Prior to joining Graphcore, Phil worked for Cray Inc. in a number of roles, including leading their engagement with the weather forecasting and climate research customers worldwide and as a technical architect. Phil holds a PhD in Computational Chemistry from the University of Bristol.

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Phil Brown

VP, Scaled Systems Product
Graphcore

Phil leads Graphcore’s efforts to build large scale AI/ML processing capability using Graphcore unique Intelligence Processing Units (IPUs) and IPU-Fabric and Streaming Memory technology. Previously he has held a number of different roles at Graphcore including Director of Applications, leading development of Graphcore’s flagship AL/ML models, and Director of Field Engineering, which acts as the focal point for technical engagements with our customers. Prior to joining Graphcore, Phil worked for Cray Inc. in a number of roles, including leading their engagement with the weather forecasting and climate research customers worldwide and as a technical architect. Phil holds a PhD in Computational Chemistry from the University of Bristol.

10:50 AM - 11:20 AM
Networking Break
11:20 AM - 11:45 AM
Chip Design
Developer Efficiency
Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Gordon Wilson

Co-Founder & CEO
Rain Neuromorphics
... read more

Gordon Wilson

Co-Founder & CEO
Rain Neuromorphics
11:45 AM - 12:10 PM

In this keynote, Dr. Cédric Bourrasset, AI Distinguished Expert at Atos, will reveal how Atos pioneered the successful architecture, build, and delivery of large-scale AI infrastructures. He will present a live demonstration of Atos-driven technology to illustrate new AI-driven endpoints featuring GPU and IPU workflow capabilities, featuring a global customer case study to elaborate on the current complex challenges faced by designing and manufacturing large-scale AI computing platforms. He will also leverage over 15 years of personal experience in designing and manufacturing supercomputing systems.

Developer Efficiency
Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Cedric Bourrasset

Head, High Performance AI Business Unit
Atos

Dr. Cedric Bourrasset is AI Business Leader for High Performance Computing Business Unit at Atos. He is also AI product manager for the Atos Codex AI suite, software enabling AI workloads into HPC environments as well as integrating a computer vision solution. He joined Atos in 2016 as an expert in the HPC/AI domain.

Previously, Cedric received his Ph.D. in Electronics and computer vision from the Blaise Pascal University of Clermont-Ferrand defending the dataflow model of computation for FPGA High Level Synthesis problematic in embedded machine learning applications.

... read more

Cedric Bourrasset

Head, High Performance AI Business Unit
Atos

Dr. Cedric Bourrasset is AI Business Leader for High Performance Computing Business Unit at Atos. He is also AI product manager for the Atos Codex AI suite, software enabling AI workloads into HPC environments as well as integrating a computer vision solution. He joined Atos in 2016 as an expert in the HPC/AI domain.

Previously, Cedric received his Ph.D. in Electronics and computer vision from the Blaise Pascal University of Clermont-Ferrand defending the dataflow model of computation for FPGA High Level Synthesis problematic in embedded machine learning applications.

12:10 PM - 12:35 PM

Cerebras Systems builds the fastest AI accelerators in the industry. In this talk we will review how the size and scope of massive natural language processing (NLP) presents fundamental challenges to legacy compute and to traditional cloud providers. We will explore the importance of guaranteed node to node latency in large clusters, how that can’t be achieved in the cloud, and how it prevents linear and even deterministic scaling. We will examine the complexity of distributing NLP models over hundreds or thousands of GPUs and show how quickly and easily a cluster of Cerebras CS-2s is set up, and how linear scaling can be achieved over millions of compute cores with Cerebras technology. And finally, we will show how innovative customers are using clusters of Cerebras CS-2s to train large language models in order to solve both basic and applied scientific challenges, including understanding the COVID-19 replication mechanism, epigenetic language modelling for drug discovery, and in the development of clean energy. This enables researchers to test ideas that may otherwise languish for lack of resources and, ultimately, reduces the cost of curiosity.

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

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Andy Hock

VP, Product Management
Cerebras

Dr. Andy Hock is VP of Product Management at Cerebras Systems with responsibility for product strategy. His organization drives engagement with engineering and our customers to inform the hardware, software, and machine learning technical requirements and accelerate world-leading AI with Cerebras’ products. Prior to Cerebras, Andy has held senior leadership positions with Arete Associates, Skybox Imaging (acquired by Google), and Google. He holds a PhD in Geophysics and Space Physics from UCLA.

12:35 PM - 1:50 PM
Lunch
1:50 PM - 2:30 PM

As scientific and machine learning workloads converge in the world of HPC, and supercomputing centers gear up for the era of exascale computing, discussions on heterogeneous systems design abound. HPC leaders increasingly need to support converged application workloads that extend beyond AI/HPC to include other computational kernels/patterns like data analytics, graph algorithms, and uncertainty quantification. In this sector, the value of heterogeneity in systems design is clear and promising, even if the method for executing these concepts is still to be determined.

However, in many industrial sectors, enterprise end customers simply use the 'threat' of heterogeneity as a tool to extract some discount from their main/incumbent vendor. The job of IT is hard enough, planning for compute, storage and networking needs, that adding a lot of compute specialization is often not high on a CIO’s priority list. 

So, who cares about heterogeneity? Where will heterogeneity in systems design change the game, and what will be its level and quality? 

Chip Design
ML at Scale
Novel AI Hardware
Systems Design
Hardware Engineering
Strategy
Systems Engineering

Author:

Wahid Bhimji

Acting Group Lead, Data & Analytics
NERSC

Wahid Bhimji is acting Group Lead and a Big Data Architect in the Data and Analytics Services Group at NERSC. His interests include machine learning and data management. Recently he led several projects applying AI for science including deep learning at scale, generative models and probabilistic programming. He coordinates aspects of machine learning deployment for the Lab's CS-Area and NERSC: including the upcoming Perlmutter HPC system and plans for future NERSC machines. Previously he was user lead for the commissioning of Cori Phase 1, particularly data services, and for the Burst Buffer. Wahid has worked for many years in Scientific Computing and Data Analysis in Academia and the U.K. Government and has a Ph.D. in High-Energy Particle Physics.

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Wahid Bhimji

Acting Group Lead, Data & Analytics
NERSC

Wahid Bhimji is acting Group Lead and a Big Data Architect in the Data and Analytics Services Group at NERSC. His interests include machine learning and data management. Recently he led several projects applying AI for science including deep learning at scale, generative models and probabilistic programming. He coordinates aspects of machine learning deployment for the Lab's CS-Area and NERSC: including the upcoming Perlmutter HPC system and plans for future NERSC machines. Previously he was user lead for the commissioning of Cori Phase 1, particularly data services, and for the Burst Buffer. Wahid has worked for many years in Scientific Computing and Data Analysis in Academia and the U.K. Government and has a Ph.D. in High-Energy Particle Physics.

Author:

Weifeng Zhang

Chief Scientist, Heterogeneous Computing
Alibaba

Weifeng Zhang is the Chief Scientist of Heterogeneous Computing at Alibaba Cloud Infrastructure, responsible for performance optimization of large scale distributed applications at the data centers. Weifeng also leads the effort to build the acceleration platform for various ML workloads via heterogeneous resource pooling based on the compiler technology. Prior to joining Alibaba, Weifeng was a Director of Engineering at Qualcomm Inc, focusing on GPU compiler and performance optimizations. Weifeng received his B.Sc. from Wuhan University, China and PhD in Computer Science from University of California, San Diego.

... read more

Weifeng Zhang

Chief Scientist, Heterogeneous Computing
Alibaba

Weifeng Zhang is the Chief Scientist of Heterogeneous Computing at Alibaba Cloud Infrastructure, responsible for performance optimization of large scale distributed applications at the data centers. Weifeng also leads the effort to build the acceleration platform for various ML workloads via heterogeneous resource pooling based on the compiler technology. Prior to joining Alibaba, Weifeng was a Director of Engineering at Qualcomm Inc, focusing on GPU compiler and performance optimizations. Weifeng received his B.Sc. from Wuhan University, China and PhD in Computer Science from University of California, San Diego.

Author:

Cedric Bourrasset

Head, High Performance AI Business Unit
Atos

Dr. Cedric Bourrasset is AI Business Leader for High Performance Computing Business Unit at Atos. He is also AI product manager for the Atos Codex AI suite, software enabling AI workloads into HPC environments as well as integrating a computer vision solution. He joined Atos in 2016 as an expert in the HPC/AI domain.

Previously, Cedric received his Ph.D. in Electronics and computer vision from the Blaise Pascal University of Clermont-Ferrand defending the dataflow model of computation for FPGA High Level Synthesis problematic in embedded machine learning applications.

... read more

Cedric Bourrasset

Head, High Performance AI Business Unit
Atos

Dr. Cedric Bourrasset is AI Business Leader for High Performance Computing Business Unit at Atos. He is also AI product manager for the Atos Codex AI suite, software enabling AI workloads into HPC environments as well as integrating a computer vision solution. He joined Atos in 2016 as an expert in the HPC/AI domain.

Previously, Cedric received his Ph.D. in Electronics and computer vision from the Blaise Pascal University of Clermont-Ferrand defending the dataflow model of computation for FPGA High Level Synthesis problematic in embedded machine learning applications.

Author:

Bhupender Thakur

Product Manager, Scientific Computing
Roche

Bhupender Thakur is Product portfolio owner for several High Performance and Big Data platforms for research and early development at Roche. He is the Agile product portfolio owner of on-premise HPC services delivering compute and storage clusters in several locations across the USA, Germany and Switzerland, and product owner for workflow applications for NGS and Oncology research supporting Roche Avenio product offerings.

Bhupender leads a cross functional squad of developers, product owners, architects and subject matter experts, working on roadmaps for existing and new research offerings and leading discussions on planning, lifecycle, operations and business continuity.

He holds a PhD in Theoretical and Computational Nuclear Physics from the University of Delaware.

... read more

Bhupender Thakur

Product Manager, Scientific Computing
Roche

Bhupender Thakur is Product portfolio owner for several High Performance and Big Data platforms for research and early development at Roche. He is the Agile product portfolio owner of on-premise HPC services delivering compute and storage clusters in several locations across the USA, Germany and Switzerland, and product owner for workflow applications for NGS and Oncology research supporting Roche Avenio product offerings.

Bhupender leads a cross functional squad of developers, product owners, architects and subject matter experts, working on roadmaps for existing and new research offerings and leading discussions on planning, lifecycle, operations and business continuity.

He holds a PhD in Theoretical and Computational Nuclear Physics from the University of Delaware.

2:30 PM - 3:15 PM

AI acceleration is a full stack effort and involves a multidisciplinary and holistic approach to design and optimization.

The field of deep learning has gained substantially from co-design concepts across the AI technology stack. The simultaneous design and optimization of hardware and software has led to new algorithms, numerical optimizations, and AI hardware. 

Looking at the AI stack for workloads like computer vision, NLP and Ads, in both a vertical and horizontal sense, there are significant opportunities and challenges for optimization through co-design. This panel will focus on software-defined chips and systems for AI (specs & evaluation, datacenter & edge) and look at the systems-level approach to co-design, including compilers and runtime etc.

Chip Design
Novel AI Hardware
Systems Design
Hardware Engineering
Software Engineering
Systems Engineering

Author:

Nick Ni

Senior Director, Datacenter AI & Compute Markets
AMD

Nick Ni is Senior Director, Data Center AI and Compute Markets at Adaptive Embedded Computing Group (AECG) at AMD, responsible for the P&L of the fast-growing Data Center AI and compute segment. His team is responsible for product marketing and product management including AI product planning, go-to-market, business development and solution architecture.

... read more

Nick Ni

Senior Director, Datacenter AI & Compute Markets
AMD

Nick Ni is Senior Director, Data Center AI and Compute Markets at Adaptive Embedded Computing Group (AECG) at AMD, responsible for the P&L of the fast-growing Data Center AI and compute segment. His team is responsible for product marketing and product management including AI product planning, go-to-market, business development and solution architecture.

Author:

Xiaoyong Liu

Director, AI Platform
Alibaba
... read more

Xiaoyong Liu

Director, AI Platform
Alibaba

Author:

Shubho Sengupta

Software Engineer
Meta

Shubho Sengupta is a Software Engineer at Meta, where he designs Meta’s Research Infra for AI training. He started working on AI in 2014, on speech related AI models like DeepSpeech and DeepVoice. Before that he pioneered many of the foundational algorithms in general purpose programming in GPUs, which has won Test of Time award. These days, he also works at the intersection of cryptography and computation, specifically in bi-partite and multi-partite matching algorithms.

... read more

Shubho Sengupta

Software Engineer
Meta

Shubho Sengupta is a Software Engineer at Meta, where he designs Meta’s Research Infra for AI training. He started working on AI in 2014, on speech related AI models like DeepSpeech and DeepVoice. Before that he pioneered many of the foundational algorithms in general purpose programming in GPUs, which has won Test of Time award. These days, he also works at the intersection of cryptography and computation, specifically in bi-partite and multi-partite matching algorithms.

Author:

Dr. Charles Fan

CEO and Co-Founder
MemVerge

Charles Fan is CEO and co-founder of MemVerge. Prior to MemVerge, Charles was the CTO of Cheetah Mobile leading its global technology teams, and an SVP/GM at VMware, founding the storage business unit that developed the Virtual SAN product. Charles also worked at EMC and was the founder of the EMC China R&D Center. Charles joined EMC via the acquisition of Rainfinity, where he was a co-founder and CTO. Charles received his Ph.D. and M.S. in Electrical Engineering from the California Institute of Technology, and his B.E. in Electrical Engineering from the Cooper Union.

... read more

Dr. Charles Fan

CEO and Co-Founder
MemVerge

Charles Fan is CEO and co-founder of MemVerge. Prior to MemVerge, Charles was the CTO of Cheetah Mobile leading its global technology teams, and an SVP/GM at VMware, founding the storage business unit that developed the Virtual SAN product. Charles also worked at EMC and was the founder of the EMC China R&D Center. Charles joined EMC via the acquisition of Rainfinity, where he was a co-founder and CTO. Charles received his Ph.D. and M.S. in Electrical Engineering from the California Institute of Technology, and his B.E. in Electrical Engineering from the Cooper Union.

Author:

Zaid Kahn

GM, Cloud AI & Advanced Systems Engineering
Microsoft

Zaid is currently GM in Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.

Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.

... read more

Zaid Kahn

GM, Cloud AI & Advanced Systems Engineering
Microsoft

Zaid is currently GM in Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.

Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.

3:15 PM - 4:00 PM

Transformers are in high demand, particularly in industries like BFSI and healthcare, for language processing, understanding, classification, generation and translation. The parameter counts for models like GPT, that are fast becoming the norm in the world of NLP, are mind-boggling, and the cost involved in training and deploying even more so. If the vast potential for LLMs is to extend beyond the wealthiest companies and research institutions on the planet, then there is a need to evaluate how to lower the barriers of entry for experimentation and research on models like GPT. There's also a need to discuss the extent to which bigger is better, in the field of practical and commercial NLP.

This panel will look at the state of play of how enterprises are using large language models today, what their plans are for future research in NLP, and how hardware & systems builders and organizations like HuggingFace can help bring state-of-the-art performance into production in smaller, more resource-constrained enterprises and labs.

Developer Efficiency
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Phil Brown

VP, Scaled Systems Product
Graphcore

Phil leads Graphcore’s efforts to build large scale AI/ML processing capability using Graphcore unique Intelligence Processing Units (IPUs) and IPU-Fabric and Streaming Memory technology. Previously he has held a number of different roles at Graphcore including Director of Applications, leading development of Graphcore’s flagship AL/ML models, and Director of Field Engineering, which acts as the focal point for technical engagements with our customers. Prior to joining Graphcore, Phil worked for Cray Inc. in a number of roles, including leading their engagement with the weather forecasting and climate research customers worldwide and as a technical architect. Phil holds a PhD in Computational Chemistry from the University of Bristol.

... read more

Phil Brown

VP, Scaled Systems Product
Graphcore

Phil leads Graphcore’s efforts to build large scale AI/ML processing capability using Graphcore unique Intelligence Processing Units (IPUs) and IPU-Fabric and Streaming Memory technology. Previously he has held a number of different roles at Graphcore including Director of Applications, leading development of Graphcore’s flagship AL/ML models, and Director of Field Engineering, which acts as the focal point for technical engagements with our customers. Prior to joining Graphcore, Phil worked for Cray Inc. in a number of roles, including leading their engagement with the weather forecasting and climate research customers worldwide and as a technical architect. Phil holds a PhD in Computational Chemistry from the University of Bristol.

Author:

Selcuk Kopru

Director, Engineering & Research, Search
eBay

Selcuk Kopru is Head of ML & NLP at eBay and is an experienced AI leader with proven expertise in creating and deploying cutting edge NLP and AI technologies and systems. He is experienced in developing scalable Machine Learning solutions to solve big data problems that involve text and multimodal data. He is also skilled in Python, Java, C++, Machine Translation and Pattern Recognition. Selcuk is also a strong research professional with a Doctor of Philosophy (PhD) in NLP in Computer Science from Middle East Technical University.

... read more

Selcuk Kopru

Director, Engineering & Research, Search
eBay

Selcuk Kopru is Head of ML & NLP at eBay and is an experienced AI leader with proven expertise in creating and deploying cutting edge NLP and AI technologies and systems. He is experienced in developing scalable Machine Learning solutions to solve big data problems that involve text and multimodal data. He is also skilled in Python, Java, C++, Machine Translation and Pattern Recognition. Selcuk is also a strong research professional with a Doctor of Philosophy (PhD) in NLP in Computer Science from Middle East Technical University.

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

... read more

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Morteza Noshad

Senior ML/NLP Scientist
Vida Health

Morteza Noshad is a senior ML/NLP scientist at Vida health. He is skilled at designing large scale NLP models for different healthcare applications such as automated clinical documentation, symptom detection and question answering. Morteza was a research scientist at Stanford University focusing on graph neural networks for clinical decision support systems where he received the SAGE Scientist Award for his research. Morteza received his Ph.D. in Computer Science from University of Michigan where he contributed to the theory of information bottleneck in deep learning. 

... read more

Morteza Noshad

Senior ML/NLP Scientist
Vida Health

Morteza Noshad is a senior ML/NLP scientist at Vida health. He is skilled at designing large scale NLP models for different healthcare applications such as automated clinical documentation, symptom detection and question answering. Morteza was a research scientist at Stanford University focusing on graph neural networks for clinical decision support systems where he received the SAGE Scientist Award for his research. Morteza received his Ph.D. in Computer Science from University of Michigan where he contributed to the theory of information bottleneck in deep learning. 

4:00 PM - 4:30 PM
Networking Break
4:30 PM - 5:10 PM
Developer Efficiency
Enterprise AI
Data Science
Software Engineering
Systems Engineering
Moderator

Author:

Carlos Guestrin

Professor, Computer Science
Stanford

Carlos Guestrin is a Professor in the Computer Science Department at Stanford University. His previous positions include the Amazon Professor of Machine Learning at the Computer Science & Engineering Department of the University of Washington, the Finmeccanica Associate Professor at Carnegie Mellon University, and the Senior Director of Machine Learning and AI at Apple, after the acquisition of Turi, Inc. (formerly GraphLab and Dato) — Carlos co-founded Turi, which developed a platform for developers and data scientist to build and deploy intelligent applications. He is a technical advisor for OctoML.ai. His team also released a number of popular open-source projects, including XGBoost, LIME, Apache TVM, MXNet, Turi Create, GraphLab/PowerGraph, SFrame, and GraphChi. Carlos received the IJCAI Computers and Thought Award and the Presidential Early Career Award for Scientists and Engineers (PECASE). He is also a recipient of the ONR Young Investigator Award, NSF Career Award, Alfred P. Sloan Fellowship, and IBM Faculty Fellowship, and was named one of the 2008 ‘Brilliant 10’ by Popular Science Magazine. Carlos’ work received awards at a number of conferences and journals, including ACL, AISTATS, ICML, IPSN, JAIR, JWRPM, KDD, NeurIPS, UAI, and VLDB. He is a former member of the Information Sciences and Technology (ISAT) advisory group for DARPA.

... read more

Carlos Guestrin

Professor, Computer Science
Stanford

Carlos Guestrin is a Professor in the Computer Science Department at Stanford University. His previous positions include the Amazon Professor of Machine Learning at the Computer Science & Engineering Department of the University of Washington, the Finmeccanica Associate Professor at Carnegie Mellon University, and the Senior Director of Machine Learning and AI at Apple, after the acquisition of Turi, Inc. (formerly GraphLab and Dato) — Carlos co-founded Turi, which developed a platform for developers and data scientist to build and deploy intelligent applications. He is a technical advisor for OctoML.ai. His team also released a number of popular open-source projects, including XGBoost, LIME, Apache TVM, MXNet, Turi Create, GraphLab/PowerGraph, SFrame, and GraphChi. Carlos received the IJCAI Computers and Thought Award and the Presidential Early Career Award for Scientists and Engineers (PECASE). He is also a recipient of the ONR Young Investigator Award, NSF Career Award, Alfred P. Sloan Fellowship, and IBM Faculty Fellowship, and was named one of the 2008 ‘Brilliant 10’ by Popular Science Magazine. Carlos’ work received awards at a number of conferences and journals, including ACL, AISTATS, ICML, IPSN, JAIR, JWRPM, KDD, NeurIPS, UAI, and VLDB. He is a former member of the Information Sciences and Technology (ISAT) advisory group for DARPA.

Author:

Sakyasingha Dasgupta

Founder & CEO
EdgeCortix

Dr. Sakyasingha Dasgupta is the founder and CEO of Edgecortix, Inc. He is an AI and machine learning technologist, entrepreneur and engineer with real-world experience in taking cutting edge research from ideation stage to scalable products. Having worked at global companies like Microsoft, IBM Research and national research labs like RIKEN and Max Planck Institute, in his more recent roles, he has helped establish and lead technology teams at lean startups in Japan and Singapore, in robotics & automation and Fintech sectors.

After spending more than a decade in research and development in diverse areas like, brain inspired computing, robotics, computer vision, hardware acceleration for AI, wearable devices, internet of things, machine learning in finance and healthcare, Sakya founded EdgeCortix, a deep-tech startup automating machine learning driven AI hardware & software co-design for an intelligent distributed edge ecosystem.

Sakyasingha recently took part in a webinar titled "Software, The Elephant in the Room for Edge AI Hardware Acceleration" - register for free to watch on-demand here

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Sakyasingha Dasgupta

Founder & CEO
EdgeCortix

Dr. Sakyasingha Dasgupta is the founder and CEO of Edgecortix, Inc. He is an AI and machine learning technologist, entrepreneur and engineer with real-world experience in taking cutting edge research from ideation stage to scalable products. Having worked at global companies like Microsoft, IBM Research and national research labs like RIKEN and Max Planck Institute, in his more recent roles, he has helped establish and lead technology teams at lean startups in Japan and Singapore, in robotics & automation and Fintech sectors.

After spending more than a decade in research and development in diverse areas like, brain inspired computing, robotics, computer vision, hardware acceleration for AI, wearable devices, internet of things, machine learning in finance and healthcare, Sakya founded EdgeCortix, a deep-tech startup automating machine learning driven AI hardware & software co-design for an intelligent distributed edge ecosystem.

Sakyasingha recently took part in a webinar titled "Software, The Elephant in the Room for Edge AI Hardware Acceleration" - register for free to watch on-demand here

Author:

Luis Ceze

Co-founder and CEO
OctoML

Luis Ceze is Co-founder and CEO at OctoML, Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington, and Venture Partner at Madrona Venture Group. His research focuses on the intersection between computer architecture, programming languages, machine learning and biology. His current focus is on approximate computing for efficient machine learning andDNA-based data storage. He co-directs the Molecular Information Systems Lab (MISL), the Systems and Architectures for Machine Learning lab (SAMPL) and the Sampa Lab for HW/SW co-design. He is a recipient of an NSF CAREER Award, a Sloan Research Fellowship, a Microsoft Research Faculty Fellowship, the IEEE TCCA young Computer Architect Award and UIUC Distinguished Alumni Award.

... read more

Luis Ceze

Co-founder and CEO
OctoML

Luis Ceze is Co-founder and CEO at OctoML, Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington, and Venture Partner at Madrona Venture Group. His research focuses on the intersection between computer architecture, programming languages, machine learning and biology. His current focus is on approximate computing for efficient machine learning andDNA-based data storage. He co-directs the Molecular Information Systems Lab (MISL), the Systems and Architectures for Machine Learning lab (SAMPL) and the Sampa Lab for HW/SW co-design. He is a recipient of an NSF CAREER Award, a Sloan Research Fellowship, a Microsoft Research Faculty Fellowship, the IEEE TCCA young Computer Architect Award and UIUC Distinguished Alumni Award.

Author:

Jian Zhang

Director, Machine Learning
SambaNova Systems
... read more

Jian Zhang

Director, Machine Learning
SambaNova Systems
5:10 PM - 5:35 PM

Theoretical metrics such as TOPS frequently fail to predict real-world AI chip performance accurately and to varying degrees, typically overpromise and underdeliver. There is a lot of angst and discussion about this root cause, but an often-overlooked culprit is the clock network, one of the largest networks on an SoC. 

The clock network can be the ultimate gating factor or enabler in data flow on a chip. Data can only move as far as one clock cycle allows. As chips grow larger and approach reticle limits, clock paths also significantly lengthen, further complicating existing clocking problems such as skew and silicon variation (at finer process geometries). An optimized clock network can streamline data flow and raise on-chip interconnect bandwidth.

Standard clock topologies that work well on small chips cannot scale to today’s very large chips. A new approach called intelligent clock networks, delivers an “ideal” clock close to the point of use, simplifying SoC designs and virtually eliminating overhead typically expended for clock distribution. Mo Faisal, the CEO and Founder of Movellus, will examine how intelligent clock networks can usher in a new era of big chip design for AI and HPC applications. Throughout his presentation, Mo will showcase how these new clock network types can help architects reach their architectural goals while generating differentiation in silicon cost and power efficiency in an already crowded market segment.

Chip Design
Novel AI Hardware
Hardware Engineering

Author:

Mo Faisal

Founder & CEO
Movellus

Prior to founding Movellus, Mo held positions at semiconductor companies including Intel and PMC Sierra. He received his B.S. from the University of Waterloo, and his M.S. and Ph.D. from the University of Michigan, and holds several patents. Mo was named a “Top 20 Entrepreneur” by the University of Michigan Zell Lurie Institute.

... read more

Mo Faisal

Founder & CEO
Movellus

Prior to founding Movellus, Mo held positions at semiconductor companies including Intel and PMC Sierra. He received his B.S. from the University of Waterloo, and his M.S. and Ph.D. from the University of Michigan, and holds several patents. Mo was named a “Top 20 Entrepreneur” by the University of Michigan Zell Lurie Institute.

5:35 PM - 6:00 PM

Many system companies are discovering that optimizing AI/ML SoC devices is a very powerful way to achieve differentiation for specific end-applications. In 2021 the semiconductor industry experienced more rounds of venture capital funding and dollars invested than ever before. What’s more, the investments in new AI companies alonewere higher than all prior yearly totals for all design types combined. Most of these new semiconductor companies targeted specific use cases of AI/ML to achieve aggressive performance, power/heat and other system objectives. Now, system companies are designing their own custom AI/ML SoCs—whether it is hyperscalers, automotive OEMs, edge or telecommunication companies–to address their own unique system-level needs.

Joe Sawicki, executive vice president, IC Siemens EDA, will explain how SoC design solutions are enabling both semiconductor and system companies to efficiently arrive at the global optimization point between power, performance, cost, yield and other factors in their AI/ML hardware designs.  All focused on achieving a holistic, optimized system-level differentiation.

Chip Design
Edge AI
Novel AI Hardware
Hardware Engineering
Systems Engineering

Author:

Joseph Sawicki

EVP, IC EDA
Siemens

Joseph Sawicki is a leading expert in IC nanometer design and manufacturing challenges. Formerly responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line, Sawicki now oversees all business units in the Siemens EDA IC segment.

Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing, and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.

 

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Joseph Sawicki

EVP, IC EDA
Siemens

Joseph Sawicki is a leading expert in IC nanometer design and manufacturing challenges. Formerly responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line, Sawicki now oversees all business units in the Siemens EDA IC segment.

Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing, and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.

 

6:00 PM - 6:30 PM
Closing Headline Keynote

Macrotrends in innovation are leveraging both software and chips to create the next round of world-changing products. Unlocking the vast potential offered by this innovation model is daunting however. Systemic complexity across all disciplines from silicon to software must be addressed in a holistic way to achieve success. AI applications change over months while chip design can take years, adding to the challenges. Talent shortages also create headwinds. And as more system companies engage in chip design, these headwinds can have a profound impact on the pace of innovation.

Complex chip and system design must be easier to achieve in less time. Sassine Ghazi will discuss several developing strategies that use AI and machine learning techniques to dramatically reduce design time and design risk, opening the opportunity for substantial increases in the pace of innovation.

Chip Design
Edge AI
Novel AI Hardware
Hardware Engineering
Systems Engineering

Author:

Sassine Ghazi

President & COO
Synopsys

Sassine Ghazi leads and drives strategy for all business units, sales and customer success, strategic alliances, marketing and communications at Synopsys. He joined the company in 1998 as an applications engineer. He then held a series of sales positions with increasing responsibility, culminating in leadership of worldwide strategic accounts. He was then appointed general manager for all digital and custom products, the largest business group in Synopsys. Under his leadership, several innovative solutions were launched in areas such as multi-die systems, AI-assisted design and silicon lifecycle management. He assumed the role of chief operating officer in August, 2020 and was appointed to the role of president in November 2021. Prior to Synopsys he was a design engineer at Intel.

 

Sassine holds a bachelor’s degree in Business Administration from Lebanese American University; a B.S.E.E from the Georgia Institute of Technology and an M.S.E.E. from the University of Tennessee.

 

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Sassine Ghazi

President & COO
Synopsys

Sassine Ghazi leads and drives strategy for all business units, sales and customer success, strategic alliances, marketing and communications at Synopsys. He joined the company in 1998 as an applications engineer. He then held a series of sales positions with increasing responsibility, culminating in leadership of worldwide strategic accounts. He was then appointed general manager for all digital and custom products, the largest business group in Synopsys. Under his leadership, several innovative solutions were launched in areas such as multi-die systems, AI-assisted design and silicon lifecycle management. He assumed the role of chief operating officer in August, 2020 and was appointed to the role of president in November 2021. Prior to Synopsys he was a design engineer at Intel.

 

Sassine holds a bachelor’s degree in Business Administration from Lebanese American University; a B.S.E.E from the Georgia Institute of Technology and an M.S.E.E. from the University of Tennessee.

 

6:30 PM - 8:00 PM
Thursday, 15 Sep, 2022
8:30 AM - 9:00 AM
Chip Design
Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Rashid Attar

Head of Engineering, Cloud/Edge AI Inference Accelerators
Qualcomm

Rashid Attar joined Qualcomm, San Deigo, CA, USA, and has involved in various aspects CDMA wireless data (EV-DO) and voice systems (IS-95, 1x-Advanced) in 1996, where he was the Project Engineer of CDMA2000-advanced from 2009 to 2013 and CDMA Modem Systems Lead at QCT from 20 through 2013. From 2014 to mid-2016, he led the ultra-low-power ASIC platform project. He is currently a Vice President Engineering with Corporate Research and Development, Qualcomm. He leads the ASIC and Hardware Department in Qualcomm Research. The Qualcomm Research portfolio consists of Communications (5G, Cellular V2X, Satellite Communications, Wi-Fi, and Industrial Internet of Things), ASIC and HW Research and Development, and Embedded IoE systems (Always on computer vision, Autonomous Driving, Robotics, and AR/VR). The ASIC and Hardware Group Research and Development portfolio consists of 5G (RFICs, PAs, Interfaces, Packaging), processors (CPUs, Programmable deep learning accelerators), ultra-low-power platform (processor, communications, memory, machine learning accelerators, power management, wireless charging), core CMOS Research and Development (3-DIC and Thermal-aware designs), and Antenna Design. He holds approximately 160 granted U.S. patents

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Rashid Attar

Head of Engineering, Cloud/Edge AI Inference Accelerators
Qualcomm

Rashid Attar joined Qualcomm, San Deigo, CA, USA, and has involved in various aspects CDMA wireless data (EV-DO) and voice systems (IS-95, 1x-Advanced) in 1996, where he was the Project Engineer of CDMA2000-advanced from 2009 to 2013 and CDMA Modem Systems Lead at QCT from 20 through 2013. From 2014 to mid-2016, he led the ultra-low-power ASIC platform project. He is currently a Vice President Engineering with Corporate Research and Development, Qualcomm. He leads the ASIC and Hardware Department in Qualcomm Research. The Qualcomm Research portfolio consists of Communications (5G, Cellular V2X, Satellite Communications, Wi-Fi, and Industrial Internet of Things), ASIC and HW Research and Development, and Embedded IoE systems (Always on computer vision, Autonomous Driving, Robotics, and AR/VR). The ASIC and Hardware Group Research and Development portfolio consists of 5G (RFICs, PAs, Interfaces, Packaging), processors (CPUs, Programmable deep learning accelerators), ultra-low-power platform (processor, communications, memory, machine learning accelerators, power management, wireless charging), core CMOS Research and Development (3-DIC and Thermal-aware designs), and Antenna Design. He holds approximately 160 granted U.S. patents

9:00 AM - 9:30 AM

 

Developer Efficiency
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Mark Russinovich

CTO, Azure
Microsoft

Mark Russinovich is Chief Technology Officer of Microsoft Azure, where he oversees the technical strategy and architecture of Microsoft’s cloud computing platform. He is a widely recognized expert in distributed systems, operating system internals, and cybersecurity. He is the author of the Jeff Aiken cyberthriller novels, Zero Day, Trojan Horse, and Rogue Code, and co-author of the Microsoft Press Windows Internals books. Russinovich joined Microsoft in 2006 when Microsoft acquired Winternals Software, the company he cofounded in 1996, as well as Sysinternals, where he authors and publishes dozens of popular Windows administration and diagnostic utilities. He is a featured speaker at major industry conferences, including Microsoft Ignite, Microsoft //build, RSA Conference, and more.

Mark recently featured in a podcast with Emerj, discussing large language models in the enterprise - check it out here

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Mark Russinovich

CTO, Azure
Microsoft

Mark Russinovich is Chief Technology Officer of Microsoft Azure, where he oversees the technical strategy and architecture of Microsoft’s cloud computing platform. He is a widely recognized expert in distributed systems, operating system internals, and cybersecurity. He is the author of the Jeff Aiken cyberthriller novels, Zero Day, Trojan Horse, and Rogue Code, and co-author of the Microsoft Press Windows Internals books. Russinovich joined Microsoft in 2006 when Microsoft acquired Winternals Software, the company he cofounded in 1996, as well as Sysinternals, where he authors and publishes dozens of popular Windows administration and diagnostic utilities. He is a featured speaker at major industry conferences, including Microsoft Ignite, Microsoft //build, RSA Conference, and more.

Mark recently featured in a podcast with Emerj, discussing large language models in the enterprise - check it out here

9:30 AM - 10:00 AM

 

Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering
Hardware Engineering

Author:

Victor Peng

President, Adaptive and Embedded Computing Group
AMD

Victor Peng is President of the Adaptive and Embedded Computing group at AMD. He is responsible for AMD’s Adaptive SmartNIC, FPGA, Adaptive SoC, embedded CPU, and embedded APU business that serve multiple market segments including the data center, communications, automotive, industrial, A&D, healthcare, test/measure/emulation, and other embedded markets. Peng also serves on the board of KLA Corporation.

Peng rejoined AMD in 2022 after 14 years at Xilinx, most recently serving as president and CEO. Prior to joining Xilinx, Peng worked at AMD as corporate vice president of silicon engineering for the graphics products group (GPG) and was the co-leader of the central silicon engineering team supporting graphics, game console products, and CPU chipsets. Prior to that, Peng held executive and engineering leadership roles at ATI, TZero Technologies, MIPS Technologies, SGI, and Digital Equipment Corp. 

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Victor Peng

President, Adaptive and Embedded Computing Group
AMD

Victor Peng is President of the Adaptive and Embedded Computing group at AMD. He is responsible for AMD’s Adaptive SmartNIC, FPGA, Adaptive SoC, embedded CPU, and embedded APU business that serve multiple market segments including the data center, communications, automotive, industrial, A&D, healthcare, test/measure/emulation, and other embedded markets. Peng also serves on the board of KLA Corporation.

Peng rejoined AMD in 2022 after 14 years at Xilinx, most recently serving as president and CEO. Prior to joining Xilinx, Peng worked at AMD as corporate vice president of silicon engineering for the graphics products group (GPG) and was the co-leader of the central silicon engineering team supporting graphics, game console products, and CPU chipsets. Prior to that, Peng held executive and engineering leadership roles at ATI, TZero Technologies, MIPS Technologies, SGI, and Digital Equipment Corp. 

10:00 AM - 10:40 AM

In developing applications for a variety of different infrastructure and hardware targets, machine learning developers face a dynamic and uncertain landscape where optimization and interoperability become challenging tasks. 

This panel will address how to build infrastructure with developer efficiency in mind, so that developers can focus on creating game-changing machine learning solutions for organizations and consumers. It will also address how hardware, systems and other technology vendors can assist in this effort.

Developer Efficiency
Enterprise AI
ML at Scale
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Ritu Goel

Director, Product Management, Adobe Sensei
Adobe

Ritu Goel is Director of Product Management at Adobe, where she has been driving strategy for AI/ML platform since its early days with the vision of democratizing AI/ML development at Adobe. Prior to this, Ritu has spent more than a decade leading product strategy and execution of various enterprise to consumer products and platforms at eBay, Macys.com and Infosys. Ritu has a bachelor of engineering from Indian Institute of Technology, Roorkee. 

... read more

Ritu Goel

Director, Product Management, Adobe Sensei
Adobe

Ritu Goel is Director of Product Management at Adobe, where she has been driving strategy for AI/ML platform since its early days with the vision of democratizing AI/ML development at Adobe. Prior to this, Ritu has spent more than a decade leading product strategy and execution of various enterprise to consumer products and platforms at eBay, Macys.com and Infosys. Ritu has a bachelor of engineering from Indian Institute of Technology, Roorkee. 

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

... read more

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Sree Ganesan

Head of Software Products
Habana Labs

Sree Ganesan leads Software Product Management at Habana Labs, working alongside a diverse global team to deliver state-of-the-art deep learning capabilities of the Habana SynapseAI® software suite to the market. Previously, she was Engineering Director in Intel’s AI Products Group, where she was responsible for AI software strategy and deep learning framework integration for Nervana NNP AI accelerators.  Ms. Ganesan joined Intel in 2001 and has held a variety of technical and management roles in software engineering, VLSI CAD and SOC design methodology. Ms. Ganesan received a bachelor’s degree in electrical engineering from the Indian Institute of Technology Madras, India and a PhD in computer engineering from the University of Cincinnati, Ohio.

... read more

Sree Ganesan

Head of Software Products
Habana Labs

Sree Ganesan leads Software Product Management at Habana Labs, working alongside a diverse global team to deliver state-of-the-art deep learning capabilities of the Habana SynapseAI® software suite to the market. Previously, she was Engineering Director in Intel’s AI Products Group, where she was responsible for AI software strategy and deep learning framework integration for Nervana NNP AI accelerators.  Ms. Ganesan joined Intel in 2001 and has held a variety of technical and management roles in software engineering, VLSI CAD and SOC design methodology. Ms. Ganesan received a bachelor’s degree in electrical engineering from the Indian Institute of Technology Madras, India and a PhD in computer engineering from the University of Cincinnati, Ohio.

Author:

Daniel Wu

Head of AI & ML, Commercial Banking
JPMorgan Chase

Daniel Wu is a technical leader who brings more than 20 years of expertise in software engineering, AI/ML, and high-impact team development. He is the Head of Commercial Banking AI and Machine Learning at JPMorgan Chase where he drives financial service transformation through AI innovation. His diverse professional background also includes building point of care expert systems for physicians to improve quality of care, co-founding an online personal finance marketplace, and building an online real estate brokerage platform.

Daniel is passionate about the democratization of technology and the ethical use of AI - a philosophy he shares in the computer science and AI/ML education programs he has contributed to over the years.

... read more

Daniel Wu

Head of AI & ML, Commercial Banking
JPMorgan Chase

Daniel Wu is a technical leader who brings more than 20 years of expertise in software engineering, AI/ML, and high-impact team development. He is the Head of Commercial Banking AI and Machine Learning at JPMorgan Chase where he drives financial service transformation through AI innovation. His diverse professional background also includes building point of care expert systems for physicians to improve quality of care, co-founding an online personal finance marketplace, and building an online real estate brokerage platform.

Daniel is passionate about the democratization of technology and the ethical use of AI - a philosophy he shares in the computer science and AI/ML education programs he has contributed to over the years.

10:40 AM - 11:10 AM
Networking Break
TRACK A: HARDWARE & SYSTEMS | TRACK B: MODELS & DATA
11:10 AM - 11:35 AM

Approximately one year ago, Samsung confirmed the world’s first use of AI to design a mobile processor chip. Since then, AI-driven design has been adopted across the industry at a phenomenal pace, accelerating silicon innovations to market in automotive, high-performance computing, consumer electronics, and other applications. Will this pace of innovation ultimately lead to self-designed silicon? In this sequel to the Day-1 Keynote – Enter the Era of Autonomous Design: Personalizing Chips for 1,000X More Powerful AI Compute, we will be looking at real-world examples of using AI to design chips, and reporting on the industry’s path to autonomous design.

Chip Design
Novel AI Hardware
Hardware Engineering
Industry & Investment

Author:

Stelios Diamantidis

Senior Director & Head of Autonomous Design Solutions
Synopsys

Stelios heads Synopsys' AI Solutions team in the Office of the President, where he researches and applies innovative machine-learning technology to address systemic complexity in the design and manufacturing of integrated computational systems. In 2020, Stelios launched DSO.ai™, the world’s first autonomous AI application for chip design. He has more than 20 years of experience in chip design and EDA software and has founded two companies in this space. Stelios holds an M.S. Electrical Engineering from Stanford University, California.

 

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Stelios Diamantidis

Senior Director & Head of Autonomous Design Solutions
Synopsys

Stelios heads Synopsys' AI Solutions team in the Office of the President, where he researches and applies innovative machine-learning technology to address systemic complexity in the design and manufacturing of integrated computational systems. In 2020, Stelios launched DSO.ai™, the world’s first autonomous AI application for chip design. He has more than 20 years of experience in chip design and EDA software and has founded two companies in this space. Stelios holds an M.S. Electrical Engineering from Stanford University, California.

 

Enterprise AI
ML at Scale
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Daniel Wu

Head of AI & ML, Commercial Banking
JPMorgan Chase

Daniel Wu is a technical leader who brings more than 20 years of expertise in software engineering, AI/ML, and high-impact team development. He is the Head of Commercial Banking AI and Machine Learning at JPMorgan Chase where he drives financial service transformation through AI innovation. His diverse professional background also includes building point of care expert systems for physicians to improve quality of care, co-founding an online personal finance marketplace, and building an online real estate brokerage platform.

Daniel is passionate about the democratization of technology and the ethical use of AI - a philosophy he shares in the computer science and AI/ML education programs he has contributed to over the years.

... read more

Daniel Wu

Head of AI & ML, Commercial Banking
JPMorgan Chase

Daniel Wu is a technical leader who brings more than 20 years of expertise in software engineering, AI/ML, and high-impact team development. He is the Head of Commercial Banking AI and Machine Learning at JPMorgan Chase where he drives financial service transformation through AI innovation. His diverse professional background also includes building point of care expert systems for physicians to improve quality of care, co-founding an online personal finance marketplace, and building an online real estate brokerage platform.

Daniel is passionate about the democratization of technology and the ethical use of AI - a philosophy he shares in the computer science and AI/ML education programs he has contributed to over the years.

11:40 AM - 12:05 PM

We have witnessed a big paradigm shift in how AI has affected our daily lives. While AI model training is typically done in a cloud infrastructure setting, model inferencing has grown enormously on power, area, bandwidth and memory constrained edge devices.

These inferencing workloads have varying computational and memory needs, stringent power and silicon area requirements that can be very challenging to meet. AI led innovation is affecting the next generation of embedded hardware and software design alike. This talk will illustrate the design philosophies and challenges around designing best in class AI hardware accelerators.

 

Chip Design
Novel AI Hardware
Hardware Engineering
Strategy
Systems Engineering

Author:

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems
... read more

Sriraman Chari

Fellow & Head of AI Accelerator IP Solution
Cadence Design Systems
Enterprise AI
ML at Scale
Data Science
Software Engineering
Strategy

Author:

Dr. Caiming Xiong

VP of AI Research and Applied AI
Salesforce

Dr. Caiming Xiong is VP of AI Research and Applied AI at Salesforce. Dr. Xiong holds a Ph.D. from the department of Computer Science and Engineering, University at Buffalo, SUNY and worked as a Postdoctoral Researcher Scholar at the University of California, Los Angeles (UCLA).

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Dr. Caiming Xiong

VP of AI Research and Applied AI
Salesforce

Dr. Caiming Xiong is VP of AI Research and Applied AI at Salesforce. Dr. Xiong holds a Ph.D. from the department of Computer Science and Engineering, University at Buffalo, SUNY and worked as a Postdoctoral Researcher Scholar at the University of California, Los Angeles (UCLA).

12:10 PM - 12:35 PM

This presentation, by the RISC-V founder, will highlight how RISC-V and vector compute are gaining momentum with AI and ML and computer vision and how it addresses challenges like managing power consumption, extra data movement, the need for multiple libraries, and issues with generational incompatibility. To solve these obstacles, many of the world’s largest data and device companies are turning to vector processing based on the RISC‑V Vector (RVV) 1.0 ISA.

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Hardware Engineering
Systems Engineering
Strategy

Author:

Krste Asanovic

Co-Founder & Chief Architect
SiFive

Krste is SiFive’s Chief Architect and a Co-Founder. He is also a Professor in the EECS Department at the University of California, Berkeley, where he also serves as Director of the ADEPT Lab. Krste leads the RISC‑V ISA project at Berkeley and is Chairman of the RISC‑V Foundation. He is an ACM Fellow and an IEEE Fellow. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge.

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Krste Asanovic

Co-Founder & Chief Architect
SiFive

Krste is SiFive’s Chief Architect and a Co-Founder. He is also a Professor in the EECS Department at the University of California, Berkeley, where he also serves as Director of the ADEPT Lab. Krste leads the RISC‑V ISA project at Berkeley and is Chairman of the RISC‑V Foundation. He is an ACM Fellow and an IEEE Fellow. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge.

Deep neural networks (DNNs), a subset of machine learning (ML), provide a foundation for automating conversational artificial intelligence (CAI) applications. FPGAs provide hardware acceleration enabling high-density and low latency CAI. In this presentation, we will provide an overview of CAI, data center use-cases, describe the traditional compute model and its limitations and show how an ML compute engine integrated into the Achronix FPGA can lead to 90% cost reductions for speech transcription.

 

Enterprise AI
NLP
Novel AI Hardware
ML at Scale
Data Science
Hardware Engineering
Software Engineering
Systems Engineering

Author:

Salvador Alvarez

Senior Manager, Product Planning
Achronix
  • Salvador Alvarez is the Senior Manager of Product Planning at Achronix, coordinating the research, development, and launch of new Achronix products and solutions. With over 20 years of experience in product growth, roadmap development, and competitive intelligence and analysis in the semiconductor, automotive, and edge AI industries, Sal Alvarez is a recognized expert in helping customers realize the advantages of edge AI and deep learning technology over legacy cloud AI approaches. Sal holds a B.S. in computer science and electrical engineering from the Massachusetts Institute of Technology.​
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Salvador Alvarez

Senior Manager, Product Planning
Achronix
  • Salvador Alvarez is the Senior Manager of Product Planning at Achronix, coordinating the research, development, and launch of new Achronix products and solutions. With over 20 years of experience in product growth, roadmap development, and competitive intelligence and analysis in the semiconductor, automotive, and edge AI industries, Sal Alvarez is a recognized expert in helping customers realize the advantages of edge AI and deep learning technology over legacy cloud AI approaches. Sal holds a B.S. in computer science and electrical engineering from the Massachusetts Institute of Technology.​
12:35 PM - 2:00 PM
2:00 PM - 2:45 PM

The relentless growth in the size and sophistication of AI models and data sets continues to put pressure on every aspect of AI processing systems. Advances in domain-specific architectures and hardware/software co-design have resulted in enormous increases in AI processing performance, but the industry needs even more. Memory systems and interconnects that supply data to AI processors will continue to be of critical importance, requiring additional innovation to meet the needs of future processors. Join Rambus Fellow and Distinguished Inventor, Dr. Steven Woo, as he leads a panel of technology experts in discussing the importance of improving memory and interfaces and enabling new system architectures, in the quest for greater AI/ML performance.

Chip Design
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Hardware Engineering
Strategy
Systems Engineering

Author:

Steven Woo

Fellow and Distinguished Inventor
Rambus


I was drawn to Rambus to focus on cutting edge computing technologies. Throughout my 15+ year career, I’ve helped invent, create and develop means of driving and extending performance in both hardware and software solutions. At Rambus, we are solving challenges that are completely new to the industry and occur as a response to deployments that are highly sophisticated and advanced.

As an inventor, I find myself approaching a challenge like a room filled with 100,000 pieces of a puzzle where it is my job to figure out how they all go together – without knowing what it is supposed to look like in the end. For me, the job of finishing the puzzle is as enjoyable as the actual process of coming up with a new, innovative solution.

For example, RDRAM®, our first mainstream memory architecture, implemented in hundreds of millions of consumer, computing and networking products from leading electronics companies including Cisco, Dell, Hitachi, HP, Intel, etc. We did a lot of novel things that required inventiveness – we pushed the envelope and created state of the art performance without making actual changes to the infrastructure.

I’m excited about the new opportunities as computing is becoming more and more pervasive in our everyday lives. With a world full of data, my job and my fellow inventors’ job will be to stay curious, maintain an inquisitive approach and create solutions that are technologically superior and that seamlessly intertwine with our daily lives.

After an inspiring work day at Rambus, I enjoy spending time with my family, being outdoors, swimming, and reading.

Education

  • Ph.D., Electrical Engineering, Stanford University
  • M.S. Electrical Engineering, Stanford University
  • Master of Engineering, Harvey Mudd College
  • B.S. Engineering, Harvey Mudd College
... read more

Steven Woo

Fellow and Distinguished Inventor
Rambus


I was drawn to Rambus to focus on cutting edge computing technologies. Throughout my 15+ year career, I’ve helped invent, create and develop means of driving and extending performance in both hardware and software solutions. At Rambus, we are solving challenges that are completely new to the industry and occur as a response to deployments that are highly sophisticated and advanced.

As an inventor, I find myself approaching a challenge like a room filled with 100,000 pieces of a puzzle where it is my job to figure out how they all go together – without knowing what it is supposed to look like in the end. For me, the job of finishing the puzzle is as enjoyable as the actual process of coming up with a new, innovative solution.

For example, RDRAM®, our first mainstream memory architecture, implemented in hundreds of millions of consumer, computing and networking products from leading electronics companies including Cisco, Dell, Hitachi, HP, Intel, etc. We did a lot of novel things that required inventiveness – we pushed the envelope and created state of the art performance without making actual changes to the infrastructure.

I’m excited about the new opportunities as computing is becoming more and more pervasive in our everyday lives. With a world full of data, my job and my fellow inventors’ job will be to stay curious, maintain an inquisitive approach and create solutions that are technologically superior and that seamlessly intertwine with our daily lives.

After an inspiring work day at Rambus, I enjoy spending time with my family, being outdoors, swimming, and reading.

Education

  • Ph.D., Electrical Engineering, Stanford University
  • M.S. Electrical Engineering, Stanford University
  • Master of Engineering, Harvey Mudd College
  • B.S. Engineering, Harvey Mudd College

Author:

Euicheol Lim

Research Fellow, System Architect
SK Hynix

Euicheol Lim is a Research Fellow and leader of system architecture team in memory system research, SK hynix. He received the B.S. degree and the M.S. degree from Yonsei University, Seoul, Korea, in 1993 and 1995, and the Ph.D. degree from Sungkyunkwan University, suwon, Korea in 2006. Dr. Lim joined SK Hynix in 2016 as a system architect in memory system research. Before joining SK Hynix, he had been working as an SoC architect in Samsung Electronics and leading the architecture of most Exynos mobile SoC series. His recent interesting point is memory and storage system architecture for AI and Big data system with various new media memory.

... read more

Euicheol Lim

Research Fellow, System Architect
SK Hynix

Euicheol Lim is a Research Fellow and leader of system architecture team in memory system research, SK hynix. He received the B.S. degree and the M.S. degree from Yonsei University, Seoul, Korea, in 1993 and 1995, and the Ph.D. degree from Sungkyunkwan University, suwon, Korea in 2006. Dr. Lim joined SK Hynix in 2016 as a system architect in memory system research. Before joining SK Hynix, he had been working as an SoC architect in Samsung Electronics and leading the architecture of most Exynos mobile SoC series. His recent interesting point is memory and storage system architecture for AI and Big data system with various new media memory.

Author:

Sumti Jairath

Chief Architect
SambaNova Systems

Sumti Jairath is Chief Architect at SambaNova Systems, with expertise in hardware-software co-design. Sumti worked on PA-RISC-based Superdome servers back at HP, followed by several generations of SPARC CMT processors at Sun Microsystems and Oracle. At Oracle, Sumti worked on SQL, Data-analytics and Machine Learning acceleration in SPARC processors. Sumti holds 27 patents in computer architecture and hardware-software co-design.

... read more

Sumti Jairath

Chief Architect
SambaNova Systems

Sumti Jairath is Chief Architect at SambaNova Systems, with expertise in hardware-software co-design. Sumti worked on PA-RISC-based Superdome servers back at HP, followed by several generations of SPARC CMT processors at Sun Microsystems and Oracle. At Oracle, Sumti worked on SQL, Data-analytics and Machine Learning acceleration in SPARC processors. Sumti holds 27 patents in computer architecture and hardware-software co-design.

Author:

Matt Fyles

SVP, Software
Graphcore

Matt Fyles is a computer scientist with over 20 years of proven experience in the design, delivery and the support of software and hardware within the microprocessor market. As SVP Software at Graphcore, Matt has built the company’s Poplar software stack from scratch, co-designed with the IPU for machine intelligence. He currently oversees the Software team’s work on the Poplar SDK, helping to support Graphcore’s growing community of developers.

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Matt Fyles

SVP, Software
Graphcore

Matt Fyles is a computer scientist with over 20 years of proven experience in the design, delivery and the support of software and hardware within the microprocessor market. As SVP Software at Graphcore, Matt has built the company’s Poplar software stack from scratch, co-designed with the IPU for machine intelligence. He currently oversees the Software team’s work on the Poplar SDK, helping to support Graphcore’s growing community of developers.

Edge AI
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Systems Engineering

Author:

Girish Venkataramani

Senior Director, ML Accelerators
Cruise
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Girish Venkataramani

Senior Director, ML Accelerators
Cruise

Author:

Ravi Narayanaswami

Principal MLA Architect
Cruise
... read more

Ravi Narayanaswami

Principal MLA Architect
Cruise

Author:

Prasun Raha

Head of HW Platform Architecture
Rivian
... read more

Prasun Raha

Head of HW Platform Architecture
Rivian

Author:

Nikunj Kotecha

Solutions Architect
BrainChip

Nikunj Kotecha is a Machine Learning Solutions Architect at BrainChip Inc. Currently, he works on developing and optimizing Machine Learning algorithms for the AkidaTM neuromorphic hardware. He also demonstrating capabilities of AkidaTM to client and supports with their neuromorphic solutions for AkidaTM. He has a Master of Science in Computer Science, where he specialized in concepts of Artificial intelligence with Deep Learning algorithms. At the time, he was a part of the Machine Learning lab and has published technical papers, supported research into different avenues of AI. He published research on Cross-Modal Fusion with Transformer architecture for Sign Language translation during the completion of his Masters. He has also worked at Oracle, where he build and integrated Machine Learning solutions to provide operational benefits of using Oracle Clinical Trial software.

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Nikunj Kotecha

Solutions Architect
BrainChip

Nikunj Kotecha is a Machine Learning Solutions Architect at BrainChip Inc. Currently, he works on developing and optimizing Machine Learning algorithms for the AkidaTM neuromorphic hardware. He also demonstrating capabilities of AkidaTM to client and supports with their neuromorphic solutions for AkidaTM. He has a Master of Science in Computer Science, where he specialized in concepts of Artificial intelligence with Deep Learning algorithms. At the time, he was a part of the Machine Learning lab and has published technical papers, supported research into different avenues of AI. He published research on Cross-Modal Fusion with Transformer architecture for Sign Language translation during the completion of his Masters. He has also worked at Oracle, where he build and integrated Machine Learning solutions to provide operational benefits of using Oracle Clinical Trial software.

Author:

David Tai

Senior Staff Engineer
DiDi Autonomous Driving
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David Tai

Senior Staff Engineer
DiDi Autonomous Driving
2:50 PM - 3:30 PM
Chip Design
ML at Scale
Novel AI Hardware
Systems Design
Hardware Engineering
Strategy
Systems Engineering

Author:

Nitza Basoco

VP, Business Development
proteanTecs

Nitza Basoco is a technology leader with over 20 years of semiconductor experience. At proteanTecs, she leads the Business Development team, responsible for driving partnership strategies and building value-add ecosystem growth. 

Previously, Nitza was the VP of Operations at Synaptics with responsibility for growing and scaling their worldwide test development, product engineering and manufacturing departments. Prior to Synaptics, Nitza spent a decade holding various leadership positions within the operations organization at MaxLinear, ranging from test development engineering to supply chain. Earlier in her career, Nitza served as a Principal Test Development Engineer for Broadcom Corporation and as a Broadband Applications Engineer at Teradyne.  

Nitza holds MEng and BSEE degrees from Massachusetts Institute of Technology.

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Nitza Basoco

VP, Business Development
proteanTecs

Nitza Basoco is a technology leader with over 20 years of semiconductor experience. At proteanTecs, she leads the Business Development team, responsible for driving partnership strategies and building value-add ecosystem growth. 

Previously, Nitza was the VP of Operations at Synaptics with responsibility for growing and scaling their worldwide test development, product engineering and manufacturing departments. Prior to Synaptics, Nitza spent a decade holding various leadership positions within the operations organization at MaxLinear, ranging from test development engineering to supply chain. Earlier in her career, Nitza served as a Principal Test Development Engineer for Broadcom Corporation and as a Broadband Applications Engineer at Teradyne.  

Nitza holds MEng and BSEE degrees from Massachusetts Institute of Technology.

Author:

Judy Priest

Distinguished Engineer & VP, GM
Microsoft

Judy Priest is a Distinguished Engineer in Microsoft's Cloud and AI Group. She drives innovation, integration, and operations in next generation Data Center platforms supporting Azure, AI, and MS's Enterprise software. Judy has over 25 years of experience in developing data centers systems and silicon, high speed signaling technologies and optics, circuit design, and physical architectures for compute, storage, graphics, and networking.

Judy has previously worked at Cisco Systems, Silicon Graphics, Hewlett-Packard, and Digital Equipment Corporation, as well as two startup ventures. She serves on the Board of Directors for Women's Audio Mission, a local SF nonprofit moving the needle for girls, women, and GNC individuals in STEM through music. Judy was awarded Business Insider's 2018 Most Powerful Female Engineers and InterCon Networking's 2020 Top 100 Leaders in Engineering.

 

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Judy Priest

Distinguished Engineer & VP, GM
Microsoft

Judy Priest is a Distinguished Engineer in Microsoft's Cloud and AI Group. She drives innovation, integration, and operations in next generation Data Center platforms supporting Azure, AI, and MS's Enterprise software. Judy has over 25 years of experience in developing data centers systems and silicon, high speed signaling technologies and optics, circuit design, and physical architectures for compute, storage, graphics, and networking.

Judy has previously worked at Cisco Systems, Silicon Graphics, Hewlett-Packard, and Digital Equipment Corporation, as well as two startup ventures. She serves on the Board of Directors for Women's Audio Mission, a local SF nonprofit moving the needle for girls, women, and GNC individuals in STEM through music. Judy was awarded Business Insider's 2018 Most Powerful Female Engineers and InterCon Networking's 2020 Top 100 Leaders in Engineering.

 

Author:

Shivam Bharuka

Software Production Engineer
Meta

Shivam is an engineering leader with Meta as part of the AI Infrastructure team for the last three years. During this time, he has helped scale the machine learning training infrastructure at Meta to support large scale ranking and recommendation models, serving more than a billion users. He is responsible for driving performance, reliability, and efficiency-oriented designs across the components of the ML training stack at Meta. Shivam holds a B.S. and an M.S. in Computer Engineering from the University of Illinois at Urbana-Champaign.

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Shivam Bharuka

Software Production Engineer
Meta

Shivam is an engineering leader with Meta as part of the AI Infrastructure team for the last three years. During this time, he has helped scale the machine learning training infrastructure at Meta to support large scale ranking and recommendation models, serving more than a billion users. He is responsible for driving performance, reliability, and efficiency-oriented designs across the components of the ML training stack at Meta. Shivam holds a B.S. and an M.S. in Computer Engineering from the University of Illinois at Urbana-Champaign.

Author:

Jim von Bergen

Senior Director, Product Quality Engineering
Cisco
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Jim von Bergen

Senior Director, Product Quality Engineering
Cisco
3:30 PM - 3:50 PM
Networking Break
3:50 PM - 4:30 PM

RISC-V adoption has increased dramatically throughout 2022, due to the architecture's simple intruction set, the ability to better pre-process NNs for acceleration and its open source nature. The advent of the RISC-V vector extension allows AI processor builders to develop on top of instructions that other companies are using and then innovate in whatever domain they want to specialize in.


Chip Design
Edge AI
ML at Scale
Novel
Systems Design
Hardware Engineering
Strategy
Systems Engineering

Author:

Bing Yu

Senior Technical Director
Andes Technology

Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

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Bing Yu

Senior Technical Director
Andes Technology

Bing Yu is a Sr. Technical Director at Andes Technology. He has over 30 years of experience in technical leadership and management, specializing in machine learning hardware, high performance CPUs and system architecture. In his current role, he is responsible for processor roadmap, architecture, and product design. Bing received his BS degree in Electrical Engineering from San Jose State University and completed the Stanford Executive Program (SEP) at the Stanford Graduate School of Business.

Edge AI
Enterprise AI
ML at Scale
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Vinesh Sukumar

Senior Director & Head of AI/ML Product Management
Qualcomm

Vinesh Sukumar currently serves as Senior Director – Head of AI/ML product management at Qualcomm Technologies, Inc (QTI).  In this role, he leads AI product definition, strategy and solution deployment across multiple business units.

•He has about 20 years of industry experience spread across research, engineering and application deployment. He currently holds a doctorate degree specializing in imaging and vision systems while also completing a business degree focused on strategy and marketing. He is a regular speaker in many AI industry forums and has authored several journal papers and two technical books.

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Vinesh Sukumar

Senior Director & Head of AI/ML Product Management
Qualcomm

Vinesh Sukumar currently serves as Senior Director – Head of AI/ML product management at Qualcomm Technologies, Inc (QTI).  In this role, he leads AI product definition, strategy and solution deployment across multiple business units.

•He has about 20 years of industry experience spread across research, engineering and application deployment. He currently holds a doctorate degree specializing in imaging and vision systems while also completing a business degree focused on strategy and marketing. He is a regular speaker in many AI industry forums and has authored several journal papers and two technical books.

Author:

Barrie Mullins

VP, Product
Flex Logix

Barrie has 25+ years of experience working with edge, embedded and AI systems across multiple industries including industrial, automotive, robotics, storage, and communications. Previously, he spent a year at Blaize as head of marketing, and three years at NVIDIA where he led the Jetson Product Marketing team. Prior to NVIDIA, he held multiple roles in Xilinx, including leading product marketing and management for the Zynq product line, sales enablement, business development, customer program management and managing design services. Barrie moved to the United States in 2007 from Ireland, where he worked for Xilinx and two starts ups, Raidtec Corp. and Eurologic Systems, in the Data Storage space where he holds three patents.  

Barrie received his EE from the Munster Technological University, an ME from University College Dublin and an MBA from Santa Clara University’s Leavey School of Business. 

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Barrie Mullins

VP, Product
Flex Logix

Barrie has 25+ years of experience working with edge, embedded and AI systems across multiple industries including industrial, automotive, robotics, storage, and communications. Previously, he spent a year at Blaize as head of marketing, and three years at NVIDIA where he led the Jetson Product Marketing team. Prior to NVIDIA, he held multiple roles in Xilinx, including leading product marketing and management for the Zynq product line, sales enablement, business development, customer program management and managing design services. Barrie moved to the United States in 2007 from Ireland, where he worked for Xilinx and two starts ups, Raidtec Corp. and Eurologic Systems, in the Data Storage space where he holds three patents.  

Barrie received his EE from the Munster Technological University, an ME from University College Dublin and an MBA from Santa Clara University’s Leavey School of Business. 

Author:

Vinay Palakkode

Senior Staff ML Engineer & Manager
Rivian

“Vinay Palakkode is a senior staff machine learning engineer and manages a team of deep learning researchers and engineers at Rivian Automotive’s self-driving organization. Vinay holds a master’s degree in electrical and computer engineering from Carnegie Mellon University. He specializes in perception for robotics and high-performance computing. Vinay held prior engineering and management positions at Apple’s Technology Development Group (TDG) and Special Projects Groups (SPG).”

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Vinay Palakkode

Senior Staff ML Engineer & Manager
Rivian

“Vinay Palakkode is a senior staff machine learning engineer and manages a team of deep learning researchers and engineers at Rivian Automotive’s self-driving organization. Vinay holds a master’s degree in electrical and computer engineering from Carnegie Mellon University. He specializes in perception for robotics and high-performance computing. Vinay held prior engineering and management positions at Apple’s Technology Development Group (TDG) and Special Projects Groups (SPG).”

Author:

Vamsi Nalluri

Machine Learning HW Architect
Rivian

Vamsi is ML HW Architect at Rivian, and has 17 years of experience in the semiconductor industry working on architecture, verification, and validation.


He most recently was at Xilinx, where he has accelerated sparse neural networks to achieve 3X hardware performance improvement on the 7nm flagship technology platform from Xilinx on many of the industry standard networks like ResNetv50, Yolo and other CNN benchmarks.

Prior to that, he has architected and trained dataflow implementations of quantized and mixed precision neural networks at Intel. 

He graduated from IIT Madras with a B.Tech in Electrical Engineering and is a big tennis fan - which includes playing and watching

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Vamsi Nalluri

Machine Learning HW Architect
Rivian

Vamsi is ML HW Architect at Rivian, and has 17 years of experience in the semiconductor industry working on architecture, verification, and validation.


He most recently was at Xilinx, where he has accelerated sparse neural networks to achieve 3X hardware performance improvement on the 7nm flagship technology platform from Xilinx on many of the industry standard networks like ResNetv50, Yolo and other CNN benchmarks.

Prior to that, he has architected and trained dataflow implementations of quantized and mixed precision neural networks at Intel. 

He graduated from IIT Madras with a B.Tech in Electrical Engineering and is a big tennis fan - which includes playing and watching

Author:

Hui Wang

Machine Learning Engineer
Schlumberger
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Hui Wang

Machine Learning Engineer
Schlumberger
4:35 PM - 5:00 PM
Chip Design
Edge AI
Enterprise AI
Novel AI Hardware
Systems Design
Hardware Engineering
Software Engineering
Systems Engineering

Author:

Harshit Khaitan

Director, AI Accelerators
Meta

Harshit Khaitan is the Director of AI Accelerator at Meta where he leads building AI Accelerators for Reality labs products. Prior to Meta, he was technical lead and co-founder for the Edge Machine learning accelerators at Google, responsible for MLA in Google Pixel 4 (Neural Core) and Pixel 6 (Google Tensor SoC). He has also held individual and technical leadership positions at Google’s first Cloud TPU, Nvidia Tegra SoCs and Nvidia GPUs. He has 10+ US and international patents in On-device AI acceleration. He has a Master’s degree in Computer Engineering from North Carolina State University and a Bachelor’s degree in Electrical Engineering from Manipal Institute of Technology, India.

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Harshit Khaitan

Director, AI Accelerators
Meta

Harshit Khaitan is the Director of AI Accelerator at Meta where he leads building AI Accelerators for Reality labs products. Prior to Meta, he was technical lead and co-founder for the Edge Machine learning accelerators at Google, responsible for MLA in Google Pixel 4 (Neural Core) and Pixel 6 (Google Tensor SoC). He has also held individual and technical leadership positions at Google’s first Cloud TPU, Nvidia Tegra SoCs and Nvidia GPUs. He has 10+ US and international patents in On-device AI acceleration. He has a Master’s degree in Computer Engineering from North Carolina State University and a Bachelor’s degree in Electrical Engineering from Manipal Institute of Technology, India.

One of the biggest challenges in the US is managing the cost of healthcare.  Although we have high healthcare costs in the US, our life expectancy is still average.  In this talk we will look at some of the core causes of healthcare costs and what modern AI hardware can do to lower these costs.  We will see that faster and bigger GPUs alone will not save us.  We need detailed models to across a wide swath of our communities and perform early interventions.  We need accurate models of our world and the ability to simulate the impact of policy changes to overall healthcare costs.  We need new MIMD hardware with cores and memory architecture that keep cores fed with the right data.

Enterprise AI
ML at Scale
Systems Design
Data Science
Software Engineering
Systems Engineering

Author:

Dan McCreary

Distinguished Engineer, Graph & AI
Optum

Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.

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Dan McCreary

Distinguished Engineer, Graph & AI
Optum

Dan is a distinguished engineer in AI working on innovative database architectures including document and graph databases. He has a strong background in semantics, ontologies, NLP and search. He is a hands-on architect and like to build his own pilot applications using new technologies. Dan started the NoSQL Now! Conference (now called the Database Now! Conferences). He also co-authored the book Making Sense of NoSQL, one of the highest rated books on Amazon on the topic of NoSQL. Dan worked at Bell Labs as a VLSI circuit designer where he worked with Brian Kernighan (of K&R C). Dan also worked with Steve Jobs at NeXT Computer.

5:05 PM - 5:40 PM

As customer success stories from AI accelerator start ups starting to proliferate, and traction starting to ramp up, it is starting to become clear which ML workloads are most amenable to domain specific architectures, and which market sectors are most likely to adopt novel AI acceleration technologies. 

With one company still retaining the majority of market share in the datacenter, and the edge currently a complete wilderness, it might still be a difficult time to launch a new accelerator company. But opportunities for capturing market share across the cloud-edge continuum definitely exist! In the world of HPC, certain ML and non-ML scientific workloads have seen extraordinary, demonstrable speed ups on novel ML systems architectures, and the scientific community only sees demand for acceleration of these types of workloads growing. At the edge some AI chip companies are already shipping in volume, while new applications emerge continuously.

This panel will look at what it takes to make it in the AIHW game, what might shift the balance of power in the datacenter, and how companies can find a niche at the edge. 

Enterprise AI
Novel AI Hardware
Strategy
Industry & Investment

Author:

Brett Simpson

Co-Founder & Partner
Arete Research

Brett Simpson is a co-founder of Arete (formed in 2000) and is based in the firm's London office. He focuses on the global semiconductor component sector. Brett is a regular public speaker at industry events and after 17 years looking at the sector, has a wealth of experience to draw on. Prior to Arete, Brett spent two years at Goldman Sachs in an equity analyst role, specialising in European technology following three years with Ericsson UK, working in business development, covering all aspects of wireline and wireless telecom infrastructure.

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Brett Simpson

Co-Founder & Partner
Arete Research

Brett Simpson is a co-founder of Arete (formed in 2000) and is based in the firm's London office. He focuses on the global semiconductor component sector. Brett is a regular public speaker at industry events and after 17 years looking at the sector, has a wealth of experience to draw on. Prior to Arete, Brett spent two years at Goldman Sachs in an equity analyst role, specialising in European technology following three years with Ericsson UK, working in business development, covering all aspects of wireline and wireless telecom infrastructure.

Author:

Gayathri Radhakrishnan

Senior Director, Venture Capital - AI Fund
Micron

Gayathri Radhakrishnan is currently part of the investment team at Micron Ventures, investing from $100M AI fund. She invests in startups that are leveraging AI/ML to solve critical problems in the areas of Manufacturing, Healthcare, Automotive and AgTech. Prior to that, she brings 20 years of multi-disciplinary experience across product management, product marketing, corporate strategy, M&A and venture investments in large Fortune 500 companies such as Dell and Corning and in startups. She has also worked as an early stage investor at Earlybird Venture Capital, a premier European venture capital fund based in Germany. She has a Masters in EE from The Ohio State University and MBA from INSEAD in France. She is also a Kauffman Fellow.

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Gayathri Radhakrishnan

Senior Director, Venture Capital - AI Fund
Micron

Gayathri Radhakrishnan is currently part of the investment team at Micron Ventures, investing from $100M AI fund. She invests in startups that are leveraging AI/ML to solve critical problems in the areas of Manufacturing, Healthcare, Automotive and AgTech. Prior to that, she brings 20 years of multi-disciplinary experience across product management, product marketing, corporate strategy, M&A and venture investments in large Fortune 500 companies such as Dell and Corning and in startups. She has also worked as an early stage investor at Earlybird Venture Capital, a premier European venture capital fund based in Germany. She has a Masters in EE from The Ohio State University and MBA from INSEAD in France. She is also a Kauffman Fellow.

Author:

Karthee Madasamy

Founder & Managing Partner
MFV Partners
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Karthee Madasamy

Founder & Managing Partner
MFV Partners

Author:

Samir Kumar

GM & Managing Director
M12
Samir is a managing director at M12, leading investments globally where artificial intelligence or machine learning is a key point of leverage.
He also stewards the fund’s Vanguard Bets investment category—startups aiming for breakthroughs that will result in generational shifts in the technology landscape. Samir’s other investment focuses include quantum computing, robotics, autonomous systems, transportation and silicon—especially for AI. Samir manages a team developing theses for new technology areas and oversees the fund’s technical and scientific advisory board.
Prior to joining M12, Samir was a senior director of business development and product management in Qualcomm’s corporate R&D division. There, he led early-stage product validation, partnerships, acquisitions, and strategy for embedded machine learning, computer vision and heterogeneous computing. Samir started his career at Microsoft, where he spent several years leading product management and product planning efforts for enterprise mobility before joining Palm and Samsung.
Samir is a regular conference speaker on his investment focus areas. He has served on or moderated panels of VCs and subject matter experts at LDV Vision Summit, tinyML Summit, and Cybersec&AI Connected.
... read more

Samir Kumar

GM & Managing Director
M12
Samir is a managing director at M12, leading investments globally where artificial intelligence or machine learning is a key point of leverage.
He also stewards the fund’s Vanguard Bets investment category—startups aiming for breakthroughs that will result in generational shifts in the technology landscape. Samir’s other investment focuses include quantum computing, robotics, autonomous systems, transportation and silicon—especially for AI. Samir manages a team developing theses for new technology areas and oversees the fund’s technical and scientific advisory board.
Prior to joining M12, Samir was a senior director of business development and product management in Qualcomm’s corporate R&D division. There, he led early-stage product validation, partnerships, acquisitions, and strategy for embedded machine learning, computer vision and heterogeneous computing. Samir started his career at Microsoft, where he spent several years leading product management and product planning efforts for enterprise mobility before joining Palm and Samsung.
Samir is a regular conference speaker on his investment focus areas. He has served on or moderated panels of VCs and subject matter experts at LDV Vision Summit, tinyML Summit, and Cybersec&AI Connected.

As AI makes its way into healthcare and medical applications, the role of hardware accelerators in the successful deployment of such large AI models becomes more and more important. Nowadays large language models, such as GPT-3 and T5, offer unprecedented opportunities to solve challenging healthcare business problems like drug discovery, medical term mapping and insight generation from electronic health records. However, efficient and cost effective training, as well as deployment and maintenance of such models in production remains a challenge for healthcare industry. This presentation will review a few open challenges and opportunities in the healthcare industry and the benefits that AI hardware innovation may bring to the ML utilization.

Developer Efficiency
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Software Engineering
Strategy
Systems Engineering

Author:

Hooman Sedghamiz

Director of AI & ML
Bayer

Hooman Sedghamiz is Director of AI & ML at Bayer. He has lead algorithm development and generated valuable insights to improve medical products ranging from implantable, wearable medical and imaging devices to bioinformatics and pharmaceutical products for a variety of multinational medical companies.

He has lead projects, data science teams and developed algorithms for closed loop active medical implants (e.g. Pacemakers, cochlear and retinal implants) as well as advanced computational biology to study the time evolution of cellular networks associated with cancer , depression and other illnesses.

His experience in healthcare also extends to image processing for Computer Tomography (CT), iX-Ray (Interventional X-Ray) as well as signal processing of physiological signals such as ECG, EMG, EEG and ACC.

Recently, his team has been working on cutting edge natural language processing and developed cutting edge models to address the healthcare challenges dealing with textual data.

... read more

Hooman Sedghamiz

Director of AI & ML
Bayer

Hooman Sedghamiz is Director of AI & ML at Bayer. He has lead algorithm development and generated valuable insights to improve medical products ranging from implantable, wearable medical and imaging devices to bioinformatics and pharmaceutical products for a variety of multinational medical companies.

He has lead projects, data science teams and developed algorithms for closed loop active medical implants (e.g. Pacemakers, cochlear and retinal implants) as well as advanced computational biology to study the time evolution of cellular networks associated with cancer , depression and other illnesses.

His experience in healthcare also extends to image processing for Computer Tomography (CT), iX-Ray (Interventional X-Ray) as well as signal processing of physiological signals such as ECG, EMG, EEG and ACC.

Recently, his team has been working on cutting edge natural language processing and developed cutting edge models to address the healthcare challenges dealing with textual data.

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